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NOIL1SM0300A-QDC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
NOIL1SM0300A
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7
Programmable Gain
The amplification inside the PGA is controlled by three
SPI settings:
The PGA gain selection: 16 gain steps are selectable by
means of the GAIN_PGA<3:0> register. Selection word
0000 corresponds with gain 1.32 and selection word 1111
corresponds with gain 15.5. Table 6 gives the 16 gain
settings.
The unity gain selection of the PGA is done by the
UNITY_PGA setting. If this bit is high, the GAIN_PGA
settings are ignored.
The SEL_UNI setting is used to have more gain steps. If
this bit is low, the signal is divided by two before entering the
PGA. GAIN_PGA and UNITY_PGA settings are applied
afterwards. If the SEL_UNI bit is high, there is a unity feed
through to the PGA. This allows having a total gain range of
0.5 to 16 in 32 steps.
The amplification in the PGA is done around a pivoting
point, set by Vcal as illustrated in Figure 8. The VCAL<7:0>
setting is used to apply the Vcal voltage through an on chip
DAC
Figure 8. Effect on Histogram of PGA (gain = 4)
(Vcal is the green line)
Number of pixels
Volts
Vcal
Figure 9 continues on the example in the section, Offset
Regulation. The blue histogram is the histogram of the
image after the column amplifiers. With offset regulation an
offset of 200 mV is added to bring the signal in range of the
ADC. The black level of 1.45V is shifted to 1.65V.
The red and blue histograms have a swing of 100 mV. This
means the input range of the ADC is not completely used. By
amplifying the signal with a factor 10 by the PGA, the full
range of the ADC can be used. In this example, Vcal is set
at 1.75V (the maximum input range of the ADC) to make
sure the spread on the black level is still inside the range of
the ADC after amplification. The result after amplification
is the purple histogram.
Table 6. GAIN SETTINGS
GAIN_PGA<3.0> Gain
0000 1.32
0001 1.56
0010 1.85
0011 2.18
0100 2.58
0101 3.05
0110 3.59
0111 4.22
1000 4.9
1001 5.84
1010 6.84
1011 8.02
1100 9.38
1101 11.2
1110 13.12
1111 15.38
Figure 9. Example of PGA Operation
Number of pixels
Volts
1.45V1.65V
Vcal
1.75V
0.75V
NOIL1SM0300A
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8
Operation and Signaling
Power Supplies
Every module on chip such as column amplifiers, output
stages, digital modules, and drivers has its own power
supply and ground. Off chip the grounds can be combined,
but not all power supplies may be combined. This results in
several different power supplies, but this is required to
reduce electrical cross-talk and to improve shielding,
dynamic range, and output swing.
On chip, the ground lines of every module are kept
separate to improve shielding and electrical cross-talk
between them.
An overview of the supplies is given in Table 7 and
Table 8. Table 8 summarizes the supplies realted to the pixel
array signals, where Table 7 summarizes the supplies related
with all other modules.
Table 7. FRAME RATE PARAMETERS
Name DC Current Peak Current Typ Max Description
V
DDA
15.7 mA 50 mA 2.5 V 5% Power supply analog readout module
V
DDD
6.7 mA 50 mA 2.5 V 2.5 V Power supply digital modules
V
ADC
32.7 mA 100 mA 2.5 V 5% Power supply of ADC circuitry
V
DDO
3.5 mA 100 mA 2.5 V 5% Power supply output drivers
Table 8. OVERVIEW OF THE POWER SUPPLIES RELATED TO PIXEL SIGNALS
Name DC Current Peak Current Min Typ Max Description
V
PIX
3 mA 100 mA 2.5 V Power supply pixel array
V
RES
1 mA
10 mA 3.0 V 3.3 V 3.5 V Power supply reset drivers
V
RES_DS
1 mA
10 mA 2.8 V Power supply reset dual slope drivers
V
RES_TS
1 mA
10 mA 2.0 V Power supply reset triple slope drivers
V
MEM_H
1 mA 1 mA
3.0 V 3.3 V 3.5 V Power supply for memory element in pixel
GND
DRIVERS
0 V Ground of the pixel array drivers
The maximum currents mentioned in Table 7 and Table 8
are peak currents. All power supplies should be able to
deliver these currents except for Vmem_l, which must be
able to sink this current.
Note that no power supply filtering on chip is
implemented and that noise on these power supplies can
contribute immediately to the noise on the signal. The
voltage supplies V
PIX,
V
DDA
and V
ADC
are especially
important to be noise free.
NOIL1SM0300A
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9
Biasing
Table 9 summarizes the biasing signals required to drive
this image sensor. For optimization reasons of the biasing of
the column amplifiers with respect to power dissipation,
several biasing resistors are required. This optimization
results in an increase of signal swing and dynamic range.
Table 9. OVERVIEW OF BIAS SIGNALS
Signal
[1]
Comment Related Module DC−Level
ADC_BIAS
Connect with 10 kW to V
ADC
and decouple with 100n to GND
ADC
ADC 693 mV
PRECHARGE_BIAS
Connect with 68 kW to V
PIX
and decouple with 100 nF to
GND
DRIVERS
Pixel array precharge 567 mV
BIAS_PGA
Biasing of amplifier stage. Connect with 110 kW to V
DDA
and de-
couple with 100 nF to GND
A
PGA 650 mV
BIAS_FAST
Biasing of columns. Connect with 42 kW to V
DDA
and decouple with
100 nF to GND
A
Column amplifiers 750 mV
BIAS_SLOW
Biasing of columns. Connect with 1.5 MW to V
DDA
and decouple
with 100 nF to GND
A
Column amplifiers 450 mV
BIAS_COL
Biasing of imager core. Connect with 500 kW to V
DDA
and decouple
with 100 nF to GND
A
Column amplifiers 508 mV
1. Each biasing signal determines the operation of a corresponding module in the sense that it controls speed and dissipation.
Digital Signals
Depending on the operation mode (master or slave), the
pixel array of the image sensor requires different digital
control signals. The function of each of the signals is shown
in Table 10.
Table 10. OVERVIEW OF BIAS SIGNALS
Signal I/O Comments
LINE_VALID Digital output Indicates when valid data is at the outputs. Active high
FRAME_VALID Digital output Indicates when a valid frame is readout. Active high
INT_TIME_3 Digital I/O In master mode: Output to indicate the triple slope integration time.
In slave mode: Input to control the triple slope integration time.
Active high
INT_TIME_2 Digital I/O In master mode: Output to indicate the dual slope integration time.
In slave mode: Input to control the dual slope integration time.
Active high
INT_TIME_1 Digital I/O In master mode: Output to indicate the integration time.
In slave mode: Input to control integration time.
Active high
RESET_N Digital input Sequencer reset. Active low
CLK Digital input Readout clock (80 MHz), sine or square clock
SPI_ENABLE Digital input Enable of the SPI
SPI_CLK Digital input Clock of the SPI. (Max. 20 MHz)
SPI_DATA Digital I/O Data line of the SPI. Bidirectional pin
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

NOIL1SM0300A-QDC

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Manufacturer:
ON Semiconductor
Description:
Image Sensors LUPA300 MONO LLC48
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