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NOIL1SM0300A-QDC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
NOIL1SM0300A
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4
SENSOR ARCHITECTURE
The floor plan of the architecture is shown in Figure 4. The
image core consists of a pixel array, an X- and Y-addressing
register, pixel array drivers, and column amplifiers. The
image sensor of 640 x 480 pixels is read out in progressive
scan.
The architecture allows programmable addressing in the
x-direction in steps of 8 pixels and in the y-direction in steps
of 1 pixel. The starting point of the address is uploadable by
means of the Serial Parallel Interface (SPI).
The PGAs amplify the signal from the column and add an
offset so the signal fits in the input range of the ADC. The
four ADCs then convert the signal to the digital domain.
Pixels are selected in a 4 * 1 kernel. Every ADC samples the
signal from one of the 4 selected pixels. Sampling frequency
is 20 MHz. The digital outputs of the four ADCs are
multiplexed to one output bus operating at 80 MHz.
Figure 4. Floor Plan of the Sensor
Pixel Architecture
The LUPA300 is designed on the 6T pixel architecture.
Color Filter
The LUPA300 can also be processed with a Bayer RGB
color pattern. Pixel (0,0) has a red filter.
Figure 5. Color Filter Arrangement on the Pixels
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5
Frame Rate and Windowing
Frame Rate
The frame rate depends on the input clock, the Frame
Overhead Time (FOT) and the Row Overhead Time (ROT).
The frame period is calculated as follows
Frame period = FOT + Nr. Lines * (ROT + Nr. Pixels *
clock period)
Example: read out of the full resolution at nominal speed
(80 MHz pixel rate = 12.5 ns, GRAN<1:0>=10):
Frame period = 7.8 ms + (480 * (400 ns + 12.5 ns * 640)
= 4.039 ms => 247.6 fps.
In case the sensor operates in subsampling, the ROT is
enlarged with 8 clock periods.
Table 3. FRAME RATE PARAMETERS
Parameter Comment Clarification
FOT Frame Overhead Time
1200 clock periods for GRAN<1:0> = 11
624 clock periods for GRAN<1:0> = 10
336 clock periods for GRAN<1:0> = 01
192 clock periods for GRAN<1:0> = 00
ROT Row Overhead Time
48 clock periods for GRAN<1:0> = 11
32 clock periods for GRAN<1:0> = 10
24 clock periods for GRAN<1:0> = 01
20 clock periods for GRAN<1:0> = 00
Nr. Lines Number of lines read out each frame
Nr. Pixels Number of pixels read out each line
clock period 1/80 MHz = 12.5 ns
Windowing
Windowing is achieved by the SPI interface. The starting
point of the x- and y-address is uploadable, as well as the
window size. The minimum step size in the x-direction is 8
pixels (only multiples of 8 can be chosen as start/stop
addresses). The minimum step size in the y-direction is 1
line (every line can be addressed) in normal mode and 2 lines
in subsampling mode.
The window size in the x-direction is uploadable in
register NB_OF_PIX. The window size in the y-direction is
determined by the register FT_TIMER
Table 4. FRAME RATE PARAMETERS
Parameter Frame Rate (fps) Frame Readout (us) Comment
640 x 480 247.5 4038
640 x 240 488.3 2048 Subsampling
256 x 256 1076 929 Windowing
Analog to Digital Converter
The sensor has four 10-bit pipelined ADC on board. The
ADCs are nominally operating at 20 Msamples/s. The input
range of the ADC is between 0.75 and 1.75V. The analog
input signal is sampled at 2.1 ns delay from the rising edge
of the ADC clock.
The digital output data appears at the output at 5.5 cycles
later. This is at the 6th falling edge succeeding the sample
moment. The data is delayed by 3.7 ns with respect to this
falling edge. This is illustrated in Figure 6.
Table 5. ADC PARAMETERS
Parameter Specification
Data rate 20 Msamples/s
Input range 0.75 V − 1.75 V
Quantization 10 bit
DNL Typ. < 0.3 LSB
INL Typ. < 0.7 LSB
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6
Figure 6. ADC Timing
CLK_ADC
DUMMY
50ns
3.7ns
5.5 clock cycles
ADC_IN
D1 D2 D3 D4 D5 D6 D7 D8
D1 D2 D3 D4
ADC_OUT
<9:0>
Programmable Gain Amplifiers
The programmable gain amplifiers have two functions:
• Adding an offset to the signal to fit it into the range of
the ADC. This is controlled by the VBLACK and
VOFFSET SPI settings.
• Amplifying the signal after the offset is added.
Offset Regulation
The purpose of offset regulation is to bring the signal in
the input range of the ADC.
After the column amplifiers, the signal from the pixels has
a range from 0.1V (bright) to 1.3V (black). The input range
of the ADC is from 0.75V to 1.75V. The amount of offset
added is controlled by two SPI settings: VBLACK<7:0> and
VOFFSET<7:0>. The formula to add offset is:
Voutput = Vsignal + (Voffset - Vblack)
Note that the FPN (fixed pattern noise) of the sensor
causes a spread of about 100 mV on the dark level. To allow
FPN correction during post processing of the image, this
spread on the dark level needs to be covered by the input
range of the ADC. This is why the default settings of the SPI
are programmed to add an offset of 200 mV. This way the
dark level goes from 1.3V to 1.5V and is the FPN
information still converted by the ADC. To match the ADC
range, it is recommended to program an offset of 340 mV. To
program this offset, the Voffset and Vblack registers can be
used. Figure 7 illustrates the operation of the offset
regulation with an example. The blue histogram is the
histogram of the image taken after the column amplifiers.
Consider as an example that the device has a black level of
1.45V and a swing of 100 mV. With this swing, it fits in the
input range of the ADC, but a large part of the range of the
ADC is not used in this case. For this reason an offset is
added first, to align the black level with the input range of the
ADC. In the first step, an offset of 200 mV is added with the
default settings of VBLACK and VOFFSET. This results in
the red histogram with a average black level of 1.65V. This
means that the spread on the black level falls completely
inside the range of the ADC. In a second step, the signal is
amplified to use the full range of the ADC.
Figure 7. Offset Regulation
Number of pixels
Volts
1.45V1.65V
VADC_HIGH
1.75V
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NOIL1SM0300A-QDC

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Manufacturer:
ON Semiconductor
Description:
Image Sensors LUPA300 MONO LLC48
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