17
Table 12. Register 9 (MASTER-SLAVE Control)
Bit Name Description Hardware Reset
Software
Reset Details
9.15:13
R/W
Transmitter Test
Mode
000 = Normal Operation
001 = Transmit Waveform Test
010 = Transmit Jitter Test in
MASTER Mode
011 = Transmit Jitter Test in
SLAVE Mode
000 000 The module enters test modes
when MDI crossover is rst
disabled via bits 16.6:5.
9.12
R/W
MASTER-SLAVE
Manual Con g
Enable
1 = Enable MASTER-SLAVE
Manual con guration value in
register 9.11
0 = Disable MASTER-SLAVE
Manual con guration value in
register 9.11
0 Retain This bit takes e ect after auto-
negotiation is restarted via
bit 0.9.
9.11
R/W
MASTER-SLAVE
Con g Value
1 = Con gure PHY as MAS-
TER during MASTER-SLAVE
negotiation
0 = Con gure PHY as SLAVE
during MASTER-SLAVE nego-
tiation
1 Retain This bit takes e ect after auto-
negotiation is restarted via bit
0.9. This bit is ignored unless
bit 9.12 is 1.
9.10
R/W
Port Type 1 = Prefer PHY as MASTER
(multiport)
0 = Prefer PHY as SLAVE (single
port)
1 Retain This bit takes e ect after auto-
negotiation is restarted via bit
0.9. This bit is ignored unless
bit 9.12 is 0.
9.9
R/W
1000BASE-T Full
Duplex
1 = Advertise PHY is 1000BA-
SET-T full duplex capable
0 = Advertise PHY is not
1000BASE-T full duplex
capable
1 Retain This bit takes e ect after auto-
negotiation is restarted via
bit 0.9.
9.8
R/W
1000BASE-T Half
Duplex
1 = Advertise PHY is 100BASE-
TX full duplex capable
0 = Advertise PHY is not
100BASE-TX full duplex
capable
1 (for ABCU-
57x1-XXX)
0 (for ABCU-
57x0-XXX)0
Retain This bit takes e ect auto-
negotiation is restarted via
bit 0.9
9.7:0RO N/A to SFP
Module
00000000 00000000
