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CS5463-ISZR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
CS5463
DS678F3 13
SWITCHING CHARACTERISTICS (Continued)
Notes: 19. Pulse output timing is specified at MCLK = 4.096 MHz, E2MODE = 0, and E3MODE[1:0] = 0. Refer to
Section 5.5 Energy Pulse Output on page 17 for more information on pulse output pins.
20. Timing is proportional to the frequency of MCLK.
ABSOLUTE MAXIMUM RATINGS
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes
.
Notes: 21. VA+ and AGND must satisfy [(VA+) - (AGND)] + 6.0 V.
22. VD+ and AGND must satisfy [(VD+) - (AGND)] + 6.0 V.
23. Applies to all pins including continuous over-voltage conditions at the analog input pins.
24. Transient current of up to 100 mA will not cause SCR latch-up.
25. Maximum DC input current for a power supply pin is ±50 mA.
26. Total power dissipation, including all input currents and output currents.
Parameter Symbol Min Typ Max Unit
E1
, E2, and E3 Timing (Note 19 and 20)
Period t
period
250 - - s
Pulse Width t
pw
244 - - s
Rising Edge to Falling Edge t
3
6--s
E2
Setup to E1 and/or E3 Falling Edge t
4
1.5 - - s
E1
Falling Edge to E3 Falling Edge t
5
248 - - s
Parameter Symbol Min Typ Max Unit
DC Power Supplies (Notes 21 and 22)
Positive Digital
Positive Analog
VD+
VA+
-0.3
-0.3
-
-
+6.0
+6.0
V
V
Input Current, Any Pin Except Supplies (Notes 23, 24, 25) I
IN
--±10mA
Output Current, Any Pin Except VREFOUT I
OUT
--100mA
Power Dissipation (Note 26) P
D --500mW
Analog Input Voltage All Analog Pins V
INA
- 0.3 - (VA+) + 0.3 V
Digital Input Voltage All Digital Pins V
IND
-0.3 - (VD+) + 0.3 V
Ambient Operating Temperature T
A
-40 - 85 °C
Storage Temperature T
stg
-65 - 150 °C
Figure 2. Timing Diagram for E1, E2, and E3
CS5463
14 DS678F3
4. THEORY OF OPERATION
The CS5463 is a dual-channel analog-to-digital convert-
er (ADC) followed by a computation engine that per-
forms power calculations and energy-to-pulse
conversion. The data flow for the voltage and current
channel measurement and the power calculation algo-
rithms are depicted in Figure 3 and 4, respectively.
The analog inputs are structured with two dedicated
channels,
Voltage and Current, then optimized to simpli-
fy interfacing to various sensing elements.
The voltage-sensing element introduces a voltage
waveform on the voltage channel input VIN± and is sub-
ject to a gain of 10x. A second-order delta-sigma modu-
lator samples the amplified signal for digitization.
Simultaneously, the current-sensing element introduces
a voltage waveform on the current channel input IIN±
and is subject to two selectable gains of the program-
mable gain amplifier (PGA). The amplified signal is
sampled by a fourth-order delta-sigma modulator for
digitization. Both converters sample at a rate of
MCLK/8, the over-sampling provides a wide dynamic
range and simplified anti-alias filter design.
4.1 Digital Filters
The decimating digital filters on both channels are Sinc
3
filters followed by 4th-order IIR filters. The single-bit
data is passed to the low-pass decimation filter and out-
put at a fixed word rate. The output word is passed to an
optional IIR filter to compensate for the magnitude roll
off of the low-pass filtering operation.
An optional digital high-pass filter (
HPF in Figure 3) re-
moves any DC component from the selected signal
path. By removing the DC component from the voltage
and/or the current channel, any DC content will also be
removed from the calculated active power as well. With
both HPFs enabled the DC component will be removed
from the calculated V
RMS
and I
RMS
as well as the appar-
ent power.
When the optional HPF in either channel is disabled, an
all-pass filter (APF) is implemented. The APF has an
amplitude response that is flat within the channel band-
width and is used for matching phase in systems where
only one HPF is engaged.
4.2 Voltage and Current Measurements
The digital filter output word is then subject to a DC off-
set adjustment and a gain calibration (See Section 7.
System Calibration on page 37). The calibrated mea-
surement is available by reading the instantaneous volt-
age and current registers.
The Root Mean Square (
RMS in Figure 4) calculations
are performed on N instantaneous voltage and current
samples, V
n and In, respectively (where N is the cycle
count), using the formula:
and likewise for V
RMS
, using Vn. I
RMS
and V
RMS
are ac-
cessible by register reads, which are updated once ev-
ery cycle count (referred to as a computational cycle).
4.3 Power Measurements
The instantaneous voltage and current samples are
multiplied to obtain the instantaneous power (see Fig-
ure 3). The product is then averaged over N conver-
sions to compute active power and is used to drive
energy pulse output E1
. Energy output E2 is selectable,
providing an energy sign or a pulse output that is pro-
portional to the apparent power. Energy output E3
VOLTAGE
SINC
3
+
X
V*
gn
CURRENT
SINC
3
+
X
I*
gn
DELAY
REG
DELAY
REG
I
DCoff
*
V
DCoff
*
PGA
+
+
Configuration Register *
Digital Filter
Digital Filter
HPF
2nd Order

Modulator
4th Order

Modulator
x10
X
X
SYS
Gain
*
PC6 PC5 PC4 PC3
PC2
PC1 PC0
6
*
DENOTES REGISTER NAME.
DELAY
REG
DELAY
REG
HPF
V
Q
*
XVDEL XIDEL
012
2322
87
...
Operational Modes Register *
+
X
+
X
X
Q
*
2
MUX
X
V
*
P
*
I
*
MUX
VHPF IHPF
65
*
APF
HPF
APF
MUX
IIR
MUX
IIR
3
IIR
4
Figure 3. Data Measurement Flow Diagram.
I
RMS
I
n
n0=
N1–
N
---------------------
=
CS5463
DS678F3 15
provides a pulse output that is proportional to the reac-
tive power or apparent power. Output E3
can also be set
to display the sign of the voltage applied to the voltage
channel or the PFMON comparator output.
The apparent power (S) is the combination of the active
power and reactive power, without reference to an im-
pedance phase angle, and is calculated by the CS5463
using the following formula:
Power Factor (PF) is the active power (P
Active
) divided
by the apparent power (S)
The sign of the power factor is determined by the active
power.
The CS5463 calculates the reactive power, Q
Trig
utiliz-
ing trigonometric identities, giving the formula
Average reactive power, Q
Avg
, is generated by averag-
ing the voltage multiplied by the current with a 90°
phase
shift difference between them. The 90° phase shift is re-
alized by applying an IIR digital filter in the voltage chan-
nel to obtain quadrature voltage (see Figure 3). This
filter will give exactly -90° phase shift across all frequen-
cies, and utilizes epsilon (
) to achieve unity gain at the
line frequency.
The instantaneous quadrature voltage (V
Q
) and current
(I) samples are multiplied to obtain the instantaneous
quadrature power (Q). The product is then averaged
over N conversions, utilizing the formula
Fundamental active (P
F
) and reactive (Q
F
) power is cal-
culated by performing a discrete Fourier transform
(DFT) at the relevant frequency on the instantaneous
voltage (V) and current (I). Epsilon is used to set the fre-
quency of the internal sine (imaginary component) and
cosine (real component) waveform generator. The har-
monic active power (P
H
) is calculated by subtracting the
fundamental active power (P
F
) from the active power
(P
Active
).
The peak current (I
peak
) and peak voltage (V
peak
) are
the instantaneous current and voltage, respectively,
with the greatest magnitude detected during the last
computation cycle. Active, apparent, reactive, and fun-
damental power are updated every computation cycle.
4.4 Linearity Performance
The linearity of the V
RMS
, I
RMS
, active, reactive, and
power-factor power measurements (before calibration)
will be within ±0.1% of reading over the ranges speci-
fied, with respect to the input voltage levels required to
cause full-scale readings in the I
RMS
and V
RMS
regis-
ters. Refer to
Accuracy Specifications on page 7.
Until the CS5463 is calibrated, the
accuracy of the
CS5463 (with respect to a reference line-voltage and
line-current level on the power mains) is not guaranteed
to within ±0.1%. (See Section 7.
System Calibration on
page 37.) The accuracy of the internal calculations can
often be improved by selecting a value for the Cycle
Count Register that will cause the time duration of one
computation cycle to be equal to (or very close to) a
whole number of power-line cycles (and N must be
greater than or equal to 4000).
X
V
*
I*
RMS
V*
RMS
E1
I
*
Energy-to-pulseX
E3
+
+
X
+
I
ACoff
*
+
+
V
ACoff
*
+
E2
N
÷
N
N
÷
N
P
*
ACTIVE
N
÷
N
P
off
*
P
*
PulseRate
*
*
DENOTES REGISTER NAME.
X
S
*
Q
*
AVG
-
+
X
Inverse
X
PF
*
Q
TRIG
*
Q
*
N
÷
N
X
Figure 4. Power Calculation Flow.
SV
RMS
I
RMS
=
PF
P
Active
S
------------------
=
Q
Trig
S
2
P
Active
2
–=
Q
Avg
Q
n
n1=
N
N
------------------------ -
=
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46

CS5463-ISZR

Mfr. #:
Buy CS5463-ISZR
Manufacturer:
Cirrus Logic
Description:
Current & Power Monitors & Regulators IC Single Phase PWR/Energy
Lifecycle:
New from this manufacturer.
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