CS5463-ISZR Datasheet CS5463-ISZR, CS5463-IS | P16-P18

CS5463

16 DS678F3

5. FUNCTIONAL DESCRIPTION

5.1 Analog Inputs

The CS5463 is equipped with two fully differential input

channels. The inputs VIN

 and IIN are designated as

the voltage and current channel inputs, respectively.

The full-scale differential input voltage for the current

and voltage channel is

250 mV

5.1.1 Voltage Channel

The output of the line voltage resistive divider or trans-

former is connected to the VIN+ and VIN- input pins of

the CS5463. The voltage channel is equipped with a

10x fixed-gain amplifier. The full-scale signal level that

can be applied to the voltage channel is

250 mV. If the

input signal is a sine wave the maximum RMS voltage

at a gain 10x is:

which is approximately 70.7% of maximum peak volt-

age. The voltage channel is also equipped with a

Volt-

age Gain Register

, allowing for an additional

programmable gain of up to 4x.

5.1.2 Current Channel

The output of the current-sense resistor or transformer

is connected to the IIN+ and IIN- input pins of the

CS5463. To accommodate different current sensing el-

ements the current channel incorporates a programma-

ble gain amplifier (PGA) with two programmable input

gains.

Configuration Register bit Igain (see Table 1) de-

fines the two gain selections and corresponding maxi-

mum input-signal level.

For example, if Igain=0, the current channel’s PGA gain

is set to 10x. If the input signals are pure sinusoids with

zero phase shift, the maximum peak differential signal

on the current or voltage channel is

250 mV

. The in-

put signal levels are approximately 70.7% of maximum

peak voltage producing a full-scale energy pulse regis-

tration equal to 50% of absolute maximum energy pulse

registration. This will be discussed further in See Sec-

tion 5.5

Energy Pulse Output on page 17.

The

Current Gain Register also facilitates an additional

programmable gain of up to 4x. If an additional gain is

applied to the voltage and/or current channel, the maxi-

mum input range should be adjusted accordingly.

5.2 IIR Filters

The current and voltage channel are equipped with a

4th-order IIR filter, that is used to compensate for the

magnitude roll off of the low-pass decimation filter.

Op-

erational Mode Register

bit IIR engages the IIR filters in

both the voltage and current channels.

5.3 High-pass Filters

By removing the offset from either channel, no error

component will be generated at DC when computing the

active power. By removing the offset from both chan-

nels, no error component will be generated at DC when

computing V

RMS

, I

RMS

, and apparent power. Operation-

al Mode Register

bits VHPF and IHPF activate the HPF

in the voltage and current channel respectively. When a

high-pass filter is active in only one channel, an all-pass

filter (APF) is applied to the other channel. The APF has

an amplitude response that is flat within the channel

bandwidth and is used for matching phase in systems

where only one HPF is engaged.

5.4 Performing Measurements

The CS5463 performs measurements of instantaneous

voltage (V

) and current (I

), and calculates instanta-

neous power (P

) at an output word rate (OWR) of

where K is the clock divider selected in the

Configura-

tion Register

The RMS voltage (V

RMS

), RMS current (I

RMS

), and ac-

tive power (P

active

) are computed using N instantaneous

samples of V

, I

, and P

respectively, where N is the

value in the

Cycle Count Register and is referred to as

a “

computation cycle”. The apparent power (S) is the

product of V

RMS

and I

RMS

. A computation cycle is de-

rived from the master clock (MCLK), with frequency:

Under default conditions and with K = 1, N = 4000, and

MCLK = 4.096 MHz – the OWR = 4000 Hz and the

ComputationCycle= 1Hz.

All measurements are available as a percentage of full

scale. The format for

signed registers is a two’s comple-

ment, normalized value between -1 and +1. The format

Igain Maximum Input Range

0±250mV10x

1 ±50 mV 50x

Table 1. Current Channel PGA Setting

250mV

---------------------

176.78mV

RMS



OWR

MCLK K

1024

-----------------------------

Computation Cycle

OWR

---------------

CS5463

DS678F3 17

for unsigned registers is a normalized value between 0

and 1. A register value of

represents the maximum possible value.

At each instantaneous measurement, the CRDY bit will

be set in the

Status Register, and the INT pin will be-

come active if the CRDY bit is unmasked in the

Mask

. At the end of each computation cycle, the

DRDY bit will be set in the

Status Register, and the INT

pin will become active if the DRDY bit is unmasked in

the

Mask Register. When these bits are asserted, they

must be cleared before they can be asserted again.

If the

Cycle Count Register (N) is set to 1, all output cal-

culations are instantaneous, and DRDY, like CRDY, will

indicate when instantaneous measurements are fin-

ished. Some calculations are inhibited when the cycle

count is less than 2.

Epsilon (

) is the ratio of the input line frequency (f

) to

the sample frequency (f

) of the ADC.

where f

= MCLK / (K*1024). With MCLK = 4.096 MHz

and clock divider K = 1, f

= 4000 Hz. For the two

most-common line frequencies, 50 Hz and 60 Hz

and

respectively. Epsilon is used to set the frequency of the

internal sine/cosine reference for the fundamental ac-

tive and reactive measurements, and the gain of the 90°

phase shift (IIR) filter for the average reactive power.

5.5 Energy Pulse Output

The CS5463 provides three output pins for energy reg-

istration. By default, E1

registers active energy, E3 reg-

isters reactive energy, and E2

indicates the sign of both

active and reactive energy. (See Figure 2.

Timing Dia-

gram for E1, E2, and E3

on page13.) The E1 pulse out-

put is designed to register the Active Energy. The E2

can be set to register Apparent Energy. Table 2 defines

the pulse output mode, which is controlled by bit

E2MODE in the

Operational Mode Register.

The E3 pin can be set to register Reactive Energy (de-

fault), PFMON, Voltage Channel Sign, or Apparent En-

ergy. Table 3 defines the pulse output format, which is

controlled by bits E3MODE[1:0] in the

Operational

Mode Register.

The pulse output frequency of E1, E2, and E3 is directly

proportional to the power calculated from the input sig-

nals. The value contained in the

PulseRateE Register is

the ratio of the frequency of energy-output pulses to the

number of samples, at full scale, which defines the av-

erage frequency for the output pulses. The pulse width,

in Figure 2, is programmable through the Pulse-

Width register, and is approximately equal to:

If MCLK =

4.096 MHz, K = 1, and PulseWidth = 1, then

 0.25 ms.

5.5.1 Active Energy

The E1 pin produces active-low pulses with an output

frequency proportional to the active power. The E2

is the energy direction indicator. Positive energy is rep-

resented by E1

pin falling while the E2 is high. Negative

energy is represented by the E1

pin falling while the E2

is low. The E1 and E2 switching characteristics are

specified in Figure 2.

Timing Diagram for E1, E2, and E3

on page13.

Figure 5 illustrates the pulse output format with positive

active energy and negative reactive energy.

1–

------------------------

0.99999988

 f

=

 50 Hz 4000 Hz 0.0125==

 60 Hz 4000 Hz 0.015==

E2MODE E2 Output Mode

0 Sign of Energy

1 Apparent Energy

Table 2. E2 Pin Configuration

E3MODE1 E3MODE0 E3

OutPut Mode

0 0 Reactive Energy

01 PFMON

1 0 Voltage Channel Sign

1 1 Apparent Energy

Table 3. E3 Pin Configuration

secPulseWidth

( MCLK/K ) / 1024

------------------------------------------------



Figure 5. Active and Reactive energy pulse outputs

CS5463

18 DS678F3

The pulse output frequency of E1 is directly proportional

to the active power calculated from the input signals. To

calculate the output frequency of E1

, the following trans-

fer function can be utilized:

With MCLK = 4.096 MHz, PF = 1, and default settings,

the pulses will have an average frequency equal to the

frequency specified by

PulseRate when the input sig-

nals applied to the voltage and current channels cause

full-scale readings in the instantaneous voltage and cur-

rent registers. The maximum pulse frequency from the

pin is (MCLK/K)/2048.

5.5.2 Apparent Energy Mode

Pin E2 outputs apparent energy pulses when the Oper-

ational Mode Register

bit E2MODE = 1. Pin E3 outputs

apparent energy pulses when the

Operational Mode

bits E3MODE[1:0] = 3 (11b). Figure 6 illus-

trates the pulse output format with apparent energy on

(E2MODE = 1 and E3MODE[1:0] = 0)

The pulse output frequency of E2

(and/or E3) is directly

proportional to the apparent power calculated from the

input signals. Since apparent power is without reference

to an impedance phase angle, the following transfer

function can be utilized to calculate the output frequency

on E2

(and/or E3).

With MCLK = 4.096 MHz and default settings, the puls-

es will have an average frequency equal to the frequen-

cy specified by

PulseRate when the input signals

applied to the voltage and current channels cause

full-scale readings in the instantaneous voltage and cur-

rent registers. The maximum pulse frequency from the

(and/or E3) pin is (MCLK/K)/2048. The E2 (and/or

) pin outputs apparent energy, but has no energy di-

rection indicator.

5.5.3 Reactive Energy Mode

Reactive energy pulses are output on pin E3 by setting

bit E3MODE[1:0] = 0 (default) in the

Operational Mode

. Positive reactive energy is registered by E3

falling when E2 is high. Negative reactive energy is reg-

istered by E3

falling when E2 is low. Figure 5 on

page 17 illustrates the pulse output format with negative

reactive energy output on pin E3

and the sign of the en-

ergy on E2

. The E3 and E2 pulse output switching char-

acteristics are specified in Figure 2 on page 13.

The pulse output frequency of E3

is directly proportional

to the reactive power calculated from the input signals.

To calculate the output frequency on E3

, the following

transfer function can be utilized:

With MCLK = 4.096 MHz, PF = 0 and default settings,

the pulses will have an average frequency equal to the

frequency specified by

PulseRate when the input sig-

nals applied to the voltage and current channels cause

full-scale readings in the instantaneous voltage and cur-

rent registers. The maximum pulse frequency from the

pin is (MCLK/K)/2048.

5.5.4 Voltage Channel Sign Mode

Setting bits E3MODE[1:0] = 2 (10b) in the Operational

Mode Register

outputs the sign of the voltage channel

on pin E3

. Figure 7 illustrates the output format with volt-

age channel sign on E3

FREQ

= Average frequency of active energy E1 pulses [Hz]

VIN = rms voltage across VIN+ and VIN- [V]

VGAIN = Voltage channel gain

IIN = rms voltage across IIN+ and IIN- [V]

IGAIN = Current channel gain

PF = Power Factor

PulseRate = PulseRateE x (MCLK/K)/2048 [Hz]

VREFIN = Voltage at VREFIN pin [V]

FREQ

VIN VGAIN IIN IGAIN PF PulseRate

VREFIN

---------------------------------------------------------------------------------------------------------------------------------=

Figure 6. Apparent energy pulse outputs

FREQ

= Average frequency of apparent energy E2 and/or E3 pulses [Hz]

VIN = rms voltage across VIN+ and VIN- [V]

VGAIN = Voltage channel gain

IIN = rms voltage across IIN+ and IIN- [V]

IGAIN = Current channel gain

PulseRate = PulseRateE x (MCLK/K)/2048 [Hz]

VREFIN = Voltage at VREFIN pin [V]

FREQ

VIN VGAIN IIN IGAIN PulseRate

VREFIN

------------------------------------------------------------------------------------------------------------------=

FREQ

= Average frequency of reactive energy E3 pulses [Hz]

VIN = rms voltage across VIN+ and VIN- [V]

VGAIN = Voltage channel gain

IIN = rms voltage across IIN+ and IIN- [V]

IGAIN = Current channel gain

PQ =

PulseRate = PulseRateE x (MCLK/K)/2048 [Hz]

VREFIN = Voltage at VREFIN pin [V]

FREQ

VIN VGAIN IIN IGAIN PQ PulseRate

VREFIN

----------------------------------------------------------------------------------------------------------------------------------=

1PF

–

Figure 7. Voltage Channel Sign Pulse outputs

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P46

CS5463-ISZR

Mfr. #:

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Manufacturer:

Cirrus Logic

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Current & Power Monitors & Regulators IC Single Phase PWR/Energy

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CS5463-ISZR

CS5463-ISZR

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