CS5463
DS678F3 21
drive the device from an external clock source, XOUT
should be left unconnected while XIN is driven by the
external circuitry. There is an amplifier between XIN and
the digital section which provides CMOS level signals.
This amplifier works with sinusoidal inputs so there are
no problems with slow edge times.
The CS5463 can be driven by an external oscillator
ranging from 2.5 to 20 MHz, but the K divider value must
be set such that the internal MCLK will run somewhere
between 2.5 MHz and 5 MHz. The K divider value is set
with the K[3:0] bits in the
Configuration Register. As an
example, if XIN = MCLK = 15 MHz, and K is set to 5,
DCLK will equal 3 MHz, which is a valid value for DCLK.
5.13 Event Handler
The INT pin is used to indicate that an internal error or
event has taken place in the CS5463. Writing a logic 1
to any bit in the
Mask Register allows the corresponding
bit in the
Status Register to activate the INT pin. The in-
terrupt condition is cleared by writing a logic 1 to the bit
that has been set in the
Status Register.
The behavior of the INT
pin is controlled by the IMODE
and IINV bits of the
Configuration Register.
If the interrupt output signal format is set for either falling
or rising edge, the duration of the INT
pulse will be at
least one DCLK cycle (DCLK = MCLK/K).
5.13.1 Typical Interrupt Handler
The steps below show how interrupts can be handled.
INITIALIZATION:
1) All Status bits are cleared by writing 0xFFFFFF to
the Status Register.
2) The condition bits which will be used to generate
interrupts are then set to logic 1 in the Mask Reg-
ister.
3) Enable interrupts.
INTERRUPT HANDLER ROUTINE:
4) Read the Status Register.
5) Disable all interrupts.
6) Branch to the proper interrupt service routine.
7) Clear the Status Register by writing back the read
value in step 4.
8) Re-enable interrupt
9) Return from interrupt service routine.
This handshaking procedure ensures that any new in-
terrupts activated between steps 4 and 7 are not lost
(cleared) by step 7.
5.14 Serial Port Overview
The CS5463 incorporates a serial port transmit and re-
ceive buffer with a command decoder that interprets
one-byte (8-bit) commands as they are received. There
are four types of commands: instructions, synchroniz-
ing, register writes, and register reads (See Section
5.16
Commands on page 23).
Instructions are one byte in length and will interrupt any
instruction currently executing. Instructions do not affect
register reads currently being transmitted.
Synchronizing commands are one byte in length and
only affect the serial interface. Synchronizing com-
mands do not affect operations currently in progress.
Register writes must be followed by three bytes of data.
Register reads can return up to four bytes of data.
Commands and data are transferred most-significant bit
(MSB) first. Figure 1 on page 12, defines the serial port
timing and required sequence necessary for writing to
and reading from the serial port receive and transmit
buffer, respectively. While reading data from the serial
port, commands and data can be written simultaneous-
ly. Starting a new register read command while data is
being read will terminate the current read in progress.
This is acceptable if the remainder of the current read
data is not needed. During data reads, the serial port re-
quires input data. If a new command and data is not
sent, SYNC0 or SYNC1 must be sent.
5.14.1 Serial Port Interface
The serial port interface is a “4-wire” synchronous serial
communications interface. The interface is enabled to
start excepting SCLKs when CS
(Chip Select) is assert-
ed (logic 0). SCLK (Serial bit-clock) is a Schmitt-trigger
input that is used to strobe the data on SDI (Serial Data
In) into the receive buffer and out of the transmit buffer
onto SDO (Serial Data Out).
IMODE IINV INT Pin
0 0 Active-low Level
0 1 Active-high Level
10 Low Pulse
11 High Pulse
Table 4. Interrupt Configuration
