CS3301
DS595F3 7
ANALOG CHARACTERISTICS (CONT.)
Notes: 14. No signals operating from external power supplies should be applied to pins of the device prior to its
own supplies being established. Connecting any terminal to voltages greater than VA+ or less than VA-
may cause destructive latch-up.
15. Ratio of common mode input amplitude vs. differential mode output amplitude for a perfectly matched
common mode input signal. Characterized with a 50 Hz, 500 mV
peak
common mode sine wave applied
to the analog inputs.
16. Output impedance characteristics are primarily determined by the integrated anti-alias resistors. Values
are approximate and can vary up to +/- 10% depending on process parameters.
Parameter Symbol
CS3301
UnitMin Typ Max
Analog Input Characteristics
Input Signal Frequencies BW DC - 2000 Hz
Input Voltage Range (Signal + Vcm) x1
(Note 14) x2 - x64
V
IN
(VA-)+0.7
(VA-)+0.7
-
-
(VA+)-1.25
(VA+)-1.75
V
Full Scale Input, Differential x1
x2
x4
x8
x16
x32
x64
V
INFS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
2.5
1.25
625
312.5
156.25
78.125
V
p-p
V
p-p
V
p-p
mV
p-p
mV
p-p
mV
p-p
mV
p-p
Input Impedance, Differential Z
INDIFF
-1, 50- G, pF
Input Impedance, Common Mode Z
INCM
-1- M
Input Bias Current I
IN
- 500 1200 pA
Crosstalk, Multiplexed Inputs (Note 4)XT - -130 - dB
Common to Differential Mode Rejection (Note 4, 15)CDMR 90 100 - dB
Analog Output Characteristics
Full Scale Output, Differential V
OUT
--5V
p-p
Output Voltage Range (Signal + Vcm) V
RNG
(VA-)+0.5
-
(VA+)-0.5
V
Output Impedance (Note 16)Z
OUT
-680-
Output Impedance Drift (Note 16)Z
TC
-0.24- Ω/°C
Output Current I
OUT
- - 3.33 mA
Load Capacitance C
L
--100nF
CS3301
8 DS595F3
DIGITAL CHARACTERISTICS
Notes: 17. Device is intended to be driven with CMOS logic levels.
18. When CLK is tied to DGND, an internal oscillator provides a master clock at approximately 2 MHz. CLK
should be driven for synchronous system operation.
Parameter Symbol
CS3301
UnitMin Typ Max
Digital Characteristics
High Level Input Drive Voltage (Note 17)V
IH
0.6*VD - VD V
Low Level Input Drive Voltage (Note 17)V
IL
0.0 - 0.8 V
Input Leakage Current I
IN
-+1+10 µA
Digital Input Capacitance C
IN
-9- pF
Rise Times, Digital Inputs Except CLK t
RISE
--100ns
Fall Times, Digital Inputs Except CLK t
FALL
--100ns
Master Clock Specifications
Master Clock Frequency (Note 18)f
CLK
2.0 2.048 2.2 MHz
Master Clock Duty Cycle f
DTY
40 - 60 %
Master Clock Rise Time t
RISE
- - 25 ns
Master Clock Fall Time t
FALL
- - 25 ns
Master Clock Jitter (In-Band or Aliased In-Band) JTR
IB
--300ps
Master Clock Jitter (Out-of-Band) JTR
OB
--1 ns
0.9 * VD
0.1 * VD
t
fall
t
rise
Figure 2. Digital Input Rise and Fall Times
Gain Selection GAIN2 GAIN1 GAIN0
x1 0 0 0
x2 0 0 1
x4 0 1 0
x8 0 1 1
x16 1 0 0
x32 1 0 1
x64 1 1 0
reserved 1 1 1
Input Selection MUX1 MUX0
800 termination 0 0
INA only 1 0
INB only 0 1
INA + INB 1 1
Table 1. Digital Selections for Gain and Input Mux Control
CS3301
DS595F3 9
POWER SUPPLY CHARACTERISTICS
Notes: 19. All outputs unloaded. Analog inputs connected to the internal 800 termination. Digital inputs forced to
VD or DGND respectively.
20. Power supply rejection characterized with a 50 Hz, 400 mVp-p sine wave applied separately to each
supply.
Parameter Symbol
CS3301
UnitMin Typ Max
Power Supply Current, Normal
Analog Power Supply Current (Note 19)I
A
- 5.25 6.8 mA
Digital Power Supply Current (Note 19)I
D
- 0.2 0.25 mA
Power Supply Current, Low Power (LPWR=1)
Analog Power Supply Current (Note 19)I
A
- 3.5 4.75 mA
Digital Power Supply Current (Note 19)I
D
- 0.2 0.25 mA
Power Supply Current, Power Down (PWDN=1)
Analog Power Supply Current (Note 19)I
A
-911µA
Digital Power Supply Current (Note 19)I
D
-28 µA
Power Supply Rejection
Power Supply Rejection Ratio (Note 4, 20) PSRR 95 120 - dB

CS3301-ISZ

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Differential Amplifiers IC Geophone Lw Noise Prgmbl Gn Dfif Amp
Lifecycle:
New from this manufacturer.
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