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ADCLK944BCPZ-R7

P1-P3P4-P6P7-P9P10-P12P13-P13
ADCLK944
Rev. 0 | Page 3 of 12
SPECIFICATIONS
Typical values are given for V
CC
− V
EE
= 3.3 V and T
A
= 25°C, unless otherwise noted. Minimum and maximum values are given for the
full V
CC
− V
EE
= 3.3 V + 10% to 2.5 V − 5% and T
A
= −40°C to +85°C variation, unless otherwise noted.
CLOCK INPUTS AND OUTPUTS
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC INPUT CHARACTERISTICS
Input Common-Mode Voltage V
ICM
V
EE
+ 1.35 V
CC
− 0.1 V
Input Differential Voltage V
ID
0.4 3.4 V p-p ±1.7 V between input pins
Input Capacitance C
IN
0.4 pF
Input Resistance R
IN
Single-Ended Mode 50 Ω
Differential Mode 100 Ω
Common Mode 50 kΩ V
T
open
Input Bias Current 20 μA
DC OUTPUT CHARACTERISTICS
Output Voltage High Level V
OH
V
CC
− 1.26 V
CC
− 0.76 V Load = 50 Ω to (V
CC
− 2.0 V)
Output Voltage Low Level V
OL
V
CC
− 1.99 V
CC
− 1.54 V Load = 50 Ω to (V
CC
− 2.0 V)
Output Voltage, Single-Ended V
O
600 960 mV V
OH
− V
OL
, output static
Voltage Reference V
REF
Output Voltage (V
CC
+ 1)/2 V −500 μA to +500 μA
Output Resistance 250 Ω
TIMING CHARACTERISTICS
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
AC PERFORMANCE
Maximum Output Frequency 6.2 7.0 GHz
Differential output voltage swing > 0.8 V
(see Figure 4)
Output Rise/Fall Time t
R
35 50 75 ps 20% to 80%, measured differentially
Propagation Delay t
PD
70 100 130 ps V
ID
= 1.6 V p-p
Temperature Coefficient 75 fs/°C
Output-to-Output Skew
1
15 ps
Part-to-Part Skew 35 ps V
ID
= 1.6 V p-p
Additive Time Jitter
Integrated Random Jitter 26 fs rms BW = 12 kHz to 20 MHz, CLK = 1 GHz
Broadband Random Jitter
2
50 fs rms V
ID
= 1.6 V p-p, 8 V/ns, V
ICM
= 2 V
CLOCK OUTPUT PHASE NOISE
Absolute Phase Noise Input slew rate > 1 V/ns (see Figure 11)
f
IN
= 1 GHz −118 dBc/Hz 100 Hz offset
−135 dBc/Hz 1 kHz offset
−144 dBc/Hz 10 kHz offset
−150 dBc/Hz 100 kHz offset
−150 dBc/Hz >1 MHz offset
1
The output-to-output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
2
Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.
ADCLK944
Rev. 0 | Page 4 of 12
POWER
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Supply Voltage Requirement V
CC
− V
EE
2.375 3.63 V 3.3 V + 10% to 2.5 V − 5%
Power Supply Current Static
Negative Supply Current I
VEE
35 mA V
CC
− V
EE
= 2.5 V ± 5%
I
VEE
37 49 mA V
CC
− V
EE
= 3.3 V ± 10%
Positive Supply Current I
VCC
139 mA V
CC
− V
EE
= 2.5 V ± 5%
I
VCC
138 165 mA V
CC
− V
EE
= 3.3 V ± 10%
Power Supply Rejection
1
PSR
VCC
−3 ps/V
Output Swing Supply Rejection
2
PSR
VCC
28 dB
1
Change in t
PD
per change in V
CC
.
2
Change in output swing per change in V
CC
.
ADCLK944
Rev. 0 | Page 5 of 12
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage
V
CC
− V
EE
6.0 V
Input Voltage
CLK, CLK
V
EE
− 0.5 V to V
CC
+ 0.5 V
CLK to CLK
±1.8 V
Input Termination, V
T
to CLK, CLK
±2 V
Input Current, CLK, CLK to V
T
Pin
(CML, LVPECL Termination)
±40 mA
Maximum Voltage on Output Pins V
CC
+ 0.5 V
Maximum Output Current 35 mA
Voltage Reference (V
REF
) V
CC
to V
EE
Operating Temperature
Ambient Range −40°C to +85°C
Junction 150°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
DETERMINING JUNCTION TEMPERATURE
To determine the junction temperature on the application
printed circuit board (PCB), use the following equation:
T
J
= T
CASE
+ (Ψ
JT
× P
D
)
where:
T
J
is the junction temperature (°C).
T
CASE
is the case temperature (°C) measured by the customer at
the top center of the package.
Ψ
JT
is as indicated in Table 5.
P
D
is the power dissipation.
Values of θ
JA
are provided for package comparison and PCB
design considerations. θ
JA
can be used for a first-order approx-
imation of T
J
using the following equation:
T
J
= T
A
+ (θ
JA
× P
D
)
where T
A
is the ambient temperature (°C).
Values of θ
JB
are provided in Table 5 for package comparison
and PCB design considerations.
ESD CAUTION
THERMAL PERFORMANCE
Table 5.
Parameter Symbol Description Value
1
Unit
Junction-to-Ambient Thermal Resistance
Still Air θ
JA
Per JEDEC JESD51-2
0.0 m/sec Airflow 78 °C/W
Moving Air θ
JMA
Per JEDEC JESD51-6
1.0 m/sec Airflow 68 °C/W
2.5 m/sec Airflow 61 °C/W
Junction-to-Board Thermal Resistance θ
JB
Per JEDEC JESD51-8
Moving Air
1.0 m/sec Airflow 49 °C/W
Junction-to-Case Thermal Resistance (Die-to-Heat Sink) θ
JC
Per MIL-STD-883, Method 1012.1
Still Air
0.0 m/sec Airflow 1.5 °C/W
Junction-to-Top-of-Package Characterization Parameter Ψ
JT
Still Air Per JEDEC JESD51-2
0.0 m/sec Airflow 2.0 °C/W
1
Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the
application to determine whether they are similar to those assumed in these calculations.
P1-P3P4-P6P7-P9P10-P12P13-P13

ADCLK944BCPZ-R7

Mfr. #:
Buy ADCLK944BCPZ-R7
Manufacturer:
Analog Devices Inc.
Description:
Clock Buffer 2.5V/3.3V 4-LVPECL Outputs SiGe
Lifecycle:
New from this manufacturer.
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