ADCLK944
Rev. 0 | Page 6 of 12
08770-00
1. EXPOSED PAD MUST BE CONNECTED
TO V
EE
.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2
12
11
10
Q1
NOTES
Q1
Q2
9
Q2
1
3
4
CLK
V
REF
2
V
T
CLK
6
Q3
5
V
EE
7
Q3
8
V
CC
16
V
EE
15
Q0
14
Q0
13
V
CC
TOP VIEW
(Not to Scale)
ADCLK944
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 CLK Differential Input (Positive).
2 V
T
Center Tap. This pin provides the center tap of a 100 Ω input resistor for the CLK and CLK
inputs.
3 V
REF
Reference Voltage. This pin provides the reference voltage for biasing ac-coupled CLK and CLK
inputs.
4
CLK
Differential Input (Negative).
5, 16 V
EE
Negative Supply Pin.
6, 7
Q3
, Q3
Differential LVPECL Outputs.
8, 13 V
CC
Positive Supply Pin.
9, 10
Q2
, Q2
Differential LVPECL Outputs.
11, 12
Q1
, Q1
Differential LVPECL Outputs.
14, 15
Q0
, Q0
Differential LVPECL Outputs.
EPAD The exposed pad must be connected to V
EE
.
ADCLK944
Rev. 0 | Page 7 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
V
CC
= 3.3 V, V
EE
= 0.0 V, V
ICM
= V
REF
, T
A
= 25°C, clock outputs terminated at 50 Ω to V
CC
− 2 V, unless otherwise noted.
08770-003
CH1 300mV M 1.25ns 20.0GS/s
A CH1 36.0mV
IT 25.0ps/pt
1
Figure 3. LVPECL Differential Output Waveform at 200 MHz
0.4
0.2
0.6
0.8
1.0
1.2
1.4
1.6
DIFFERENTIAL OUTPUT VOLTAGE SWING (V)
0
0 1000 2000 3000 4000 5000 6000 7000 8000
FREQUENCY (MHz)
08770-004
3.3V
2.5V
Figure 4. Differential Output Voltage Swing vs. Frequency
80
85
90
95
100
105
110
PROPAGATION DELAY (ps)
115
0.1 0.3 0.5 0.7 0.9 1.1
DIFFERENTIAL INPUT VOLTAGE SWING (V)
08770-005
DELAY 3.3V
DELAY 2.5V
Figure 5. Propagation Delay vs. Differential Input Voltage Swing
08770-006
CH1 300mV M 250ps 20.0GS/s
A CH1 36.0mV
IT 5.0ps/pt
1
Figure 6. LVPECL Differential Output Waveform at 1000 MHz
1.55
1.50
1.45
1.40
1.35
1.30
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
DIFFERENTIAL OUTPUT VOLTAGE SWING (V)
POWER SUPPLY VOLTAGE (V)
+25°C
+85°C
–40°C
08770-009
Figure 7. Differential Output Voltage Swing vs. Power Supply Voltage
and Temperature, V
ID
= 1.6 V p-p
140
3.3V
2.5V
130
120
110
100
90
80
1.0 1.5 2.0 2.5 3.0 3.5
PROPAGATION DELAY (ps)
0-008
DC COMMON-MODE VOLTAGE (V
ICM
– V
EE
)
0877
Figure 8. Propagation Delay vs. DC Common-Mode Voltage
ADCLK944
Rev. 0 | Page 8 of 12
20
0
2.375 2.500 2.625 2.970 3.300 3.630
160
140
120
80
100
40
60
CURRENT (mA)
POWER SUPPLY VOLTAGE (V)
08770-010
–40°C
+25°C
+85°C
300
250
200
150
100
50
0
02015105
RANDOM JITTER (
f
s rms)
INPUT SLEW RATE (V/ns)
I
VCC
I
VEE
08770-012
Figure 9. Power Supply Current vs. Power Supply Voltage and Temperature,
All Outputs Loaded (50 Ω to V
CC
− 2 V)
90
–150
–140
–130
–120
–110
–100
PHASE NOISE (dBc/Hz)
–170
–160
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET (Hz)
08770-011
ADCLK944
CLOCK SOURCE
Figure 10. Absolute Phase Noise Measured at 1 GHz with Agilent E5052B
Figure 11. Random Jitter vs. Input Slew Rate, V
ID
Method

ADCLK944BCPZ-R7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Clock Buffer 2.5V/3.3V 4-LVPECL Outputs SiGe
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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