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E-TDA7590

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7 DSP peripherals
7.1 Serial audio interface (SAI)
The SAI is used to communicate between the CODEC and the DSPs.
In addition, digital audio can be directly input for processing. There is only one SAI found on
the chip that can be accessed by either the DSP or the DMA controller. The main features of
this block are listed below:
– Slave operating modes, all clock lines can be inputs or outputs
– Transmit and receive interrupt logic triggers on left/right data pairs
– Receive and transmit data registers have two locations to hold left and right data
7.2 Serial communication interface (SCI)
The serial communication interface provides a full duplex port for serial communication to
other DSPs, microprocessors, and peripherals like modems.
The interface supports the following features:
– No additional logic for connection to other TTL level peripherals
– Asynchronous bit rates and protocols "High speed“ synchronous data
transmission.
– Asynchronous protocol includes Multidrop mode for master/slave operation with
wake-up on Idle line and wake-up on address bit capability, permitting the SCI to
share a single line with multiple peripherals
– Transmit and receive logic can operate asynchronously from each other.
– A programmable baud-rate generator which provide the transmit and receive
clocks or functions as a general purpose timer.
7.3 I
2
C interface
The inter integrated-circuit bus is a simple bi-directional two-wire bus used for efficient inter
IC control. All I
2
C bus compatible devices incorporate an on-chip interface which allows
them to communicate directly with each other via the I
2
C bus.
Every component connected to the I
2
C bus has it s own unique address whether it is a CPU,
memory or some other complex function chip. Each of these chips can act as a receiver
and/or transmitter depending on it s functionality.
7.4 Host interface (HI)
The host interface is a system-on-chip module that permits connection to the data bus of a
host processor. The HI is capable of driving 16 programmable external pins which can be
configured as an 8 bit parallel port for direct connection to a host processor.
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The key features of the host interface are:
• 8 bit parallel port "Full-duplex" dedicated host register bank
• Dedicated Mozart™ core DSP register core bank.
• Register banks map directly into Mozart X memory space
• 3 transfer modes:
– host command
– Host to Mozart core DSP
– Mozart core DSP to host
• Access protocols:
– Software polled
– Interrupt
– DMA access by the Mozart core DSP core
• 2+ wait states clock cycles per transfer
• Supported instructions:
– Data transfer between Mozart core and external host using Mozart MOVE
instruction
– Simple I/O service routine with bit addressing instructions
– IO service using fast interrupts with MOVEP instructions.
7.5 ESSI
The ESSI peripheral enables serial-port communication between the DSP core and external
devices including Codecs, DSP, microprocessors. The ESSI is capable of driving 12
programmable external pins which can be configured as GPIO ports C and D or ESSI pins.
The key features of the ESSI are:
• Independent receiver and transmitter
• Synchronous or asynchronous channel modes synchronous. Receiver and transmitter
use same clock/sync asynchronous. Receiver and transmitter may use separate
clock/sync up to one transmitter enabled in asynchronous channel mode.
• Up to three transmitters enabled in synchronous channel mode.
• Normal mode. One word per period.
• Network mode. Up to 32 words per period.
7.6 EOC
The Salieri extended on-chip memory interface provides access to 40 kB of on-chip
memory. The Mozart core will treat this memory as if it were external. Access by off-chip
expansion bus masters is permitted. All accesses to the extended on-chip RAM are
controlled by the extended on-chip memory control register. This register determines which
combinations of the Address attribute pins should be interpreted as accesses to the 40 kB of
RAM.
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7.7 Timers and watchdog block
The timers and watchdog block consists of a common 21-bit prescaler and three
independent and identical general-purpose 24-bit timer/event counters, each with its own
register set.
Each timer has the following capabilities:
• Uses internal or external clocking.
• Interrupts the Mozart after a specified number of events (clocks).
• Signals an external device after counting internal events.
• Triggers DMA transfers after a specified number of events (clocks) occurs.
• Connects to the external world through designated pins TIO[0-2] for timers 0-2.
When TIO is configured as an
• Input: timer functions as an external event counter. Timer measures external pulse
width/signal period.
• Output: timer functions as a:
–Timer
– Watchdog timer
– Pulse-width modulator.
7.8 PLL
The PLL generates the following clocks:
• DCLK: DSP core clock
• DACLK: ADC and DAC clock
• LRCLK: left/right clock for the SAI and the CODEC
• SCLK: shift serial clock for the SAI and the CODEC
7.9 CODEC cell
The main features of the CODEC cell are listed below:
• 20 bits stereo DAC, and 18 bits ADC
•I
2
S format
• Oversampling ratio: 512
• Sampling rates of 8 kHz to 48 kHz
The analog interface is in the form of differential signals for each channel. The interface on
the digital side has the form of an SAI interface and can interface directly to an SAI channel
and then to the DSP core.
DCLK can be supplied either by the internal PLL or by external, to allow synchronization
with external anal digital sources.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42

E-TDA7590

Mfr. #:
Buy E-TDA7590
Manufacturer:
STMicroelectronics
Description:
Digital Signal Processors & Controllers - DSP, DSC Digital signal IC speech and audio
Lifecycle:
New from this manufacturer.
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