E-TDA7590 Datasheet E-TDA7590, E-TDA7590TR | P22-P24

Package information TDA7590

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8 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK

is an ST trademark.

Figure 3. TQFP144 mechanical data and package dimensions

OUTLINE AND

MECHANICAL DATA

DIM.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 1.20 0.047

A1 0.05 0.15 0.002 0.006

A2 0.95 1.00 1.05 0.037 0.039 0.041

B 0.17 0.22 0.27 0.007 0.009 0.011

C 0.09 0.20 0.003 0.008

D 21.80 22.00 22.20 0.858 0.866 0.874

D1 19.80 20.00 20.20 0.779 0.787 0.795

D2 2.00 0.079

D3 17.50 0.689

E 21.80 22.00 22.20 0.858 0.866 0.874

E1 19.80 20.00 20.20 0.779 0.787 0.795

E2 2.00 0.079

E3 17.50 0.689

e0.50 0.020

L 0.45 0.60 0.75 0.018 0.024 0.030

L1 1.00 0.0393

K 0˚ (min.), 3.5˚ (typ.), 7˚(max.)

ccc 0.08 0.03

TQFP144

(20x20x1.0mm exposed pad down)

7386636 B

Note 1: Exact shape of each corner is optional.

TDA7590 Appendix 1

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9 Appendix 1

9.1 Benchmarking program

;********************************* FILE HEADER *********************************

;

;Title: Salieri CODEC/SAI Functionality Test

;

;File Name: full_func.asm

;

;Author: --

;

;Language: DSP2420 Core Assembler

;

;Project: Salieri

;

;Description: CODEC + TIMER + HI gpios + ESSI + SCI

;

;;

;*******************************************************************************

;*********************************** Equates ***********************************

;*******************************************************************************

Npts equ 20

Ntaps equ 4

;------------------------------------------------------------------------

; EQUATES for I/O Port Programming

;------------------------------------------------------------------------

; Register Addresses

M_HDR EQU $FFFFC9 ; PS- Host port GPIO data Register

M_HDDR EQU $FFFFC8 ; PS- Host port GPIO direction Register

M_PCRC EQU $FFFFBF ; Port C Control Register

M_PRRC EQU $FFFFBE ; Port C Direction Register

M_PDRC EQU $FFFFBD ; Port C GPIO Data Register

M_PCRD EQU $FFFFAF ; Port D Control register

M_PRRD EQU $FFFFAE ; Port D Direction Data Register

M_PDRD EQU $FFFFAD ; Port D GPIO Data Register

M_PCRE EQU $FFFF9F ; Port E Control register

M_PRRE EQU $FFFF9E ; Port E Direction Register

M_PDRE EQU $FFFF9D ; Port E Data Register

M_OGDB EQU $FFFFFC ; OnCE GDB Register

;------------------------------------------------------------------------

; EQUATES for Exception Processing

;------------------------------------------------------------------------

; Register Addresses

IPR_C EQU $FFFFFF ; Interrupt Priority Register Core

Appendix 1 TDA7590

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IPR_P EQU $FFFFFE ; Interrupt Priority Register Peripheral

; SAI interrupt Vectors

SAI_ROF EQU $070 ; Receiver Overflow

SAI_TUF EQU $072 ; Transmitter Underflow

SAI_RDR EQU $074 ; Receiver Data Ready

SAI_TDE EQU $076 ; Transmitter Data Empty

; Timer interrupt Vector

Timer0_tcf equ $24 ; Timer0 Compare

Timer0_tof equ $26 ; Timer0 Overflow

Timer1_tcf equ $28 ; Timer1 Compare

Timer1_tof equ $2A ; Timer1 Overflow

Timer2_tcf equ $2C ; Timer2 Compare

Timer2_tof equ $2E ; Timer2 Overflow

; SCI Interrupt Vectors

SCI_REC EQU $000050 ; SCI receive data

SCI_REC_E EQU $000052 ; SCI receive data with exception status

SCI_TRANS EQU $000054 ; SCI transmit data

SCI_IDLE EQU $000056 ; SCI idle line

SCI_TIMER EQU $000058 ; SCI timer

;;; Bit Definition for SCI_SSR

FRAMING EQU 6

RESET EQU $000000 ; Reset address location

;------------------------------------------------------------------------

; EQUATES for SAI (y memory)

;------------------------------------------------------------------------

SAI_RCS EQU $FFFFFF ; SAI Receive Control/Status Register

SAI_RX2 EQU $FFFFFE ; SAI Channel 2 Receiver Data

SAI_RX1 EQU $FFFFFD ; SAI Channel 1 Receiver Data

SAI_RX0 EQU $FFFFFC ; SAI Channel 0 Receiver Data

SAI_TCS EQU $FFFFFB ; SAI Transmit Control/Status Register

SAI_TX2 EQU $FFFFFA ; SAI Channel 2 Transmitter Data

SAI_TX1 EQU $FFFFF9 ; SAI Channel 1 Transmitter Data

SAI_TX0 EQU $FFFFF8 ; SAI Channel 0 Transmitter Data

;;; Bit Definitions for M_RCS

ROFCL EQU 16 ; Receiver Data Overflow Clear

RDR EQU 15 ; Receiver Data Ready

ROFL EQU 14 ; Receiver Data Overflow

;Reserved

RXIE EQU 12 ; Receiver Interrupt Enable

RDWJ EQU 11 ; Receiver Data Word Justification

RREL EQU 10 ; Receiver Relative Timing

RCKP EQU 9 ; Receiver Clock Polarity

RLRS EQU 8 ; Receiver Left Right Selection

RDIR EQU 7 ; Receiver Data Shift Direction

RWL1 EQU 6 ; Receiver Word Length Control 1

RWL0 EQU 5 ; Receiver Word Length Control 0

;Reserved

RMME EQU 3 ; Receiver Master Mode Enable

R2EN EQU 2 ; Receiver 2 enable

R1EN EQU 1 ; Receiver 1 enable

R0EN EQU 0 ; Receiver 0 enable

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42

E-TDA7590

Mfr. #:

Buy E-TDA7590

Manufacturer:

STMicroelectronics

Description:

Digital Signal Processors & Controllers - DSP, DSC Digital signal IC speech and audio

Lifecycle:

New from this manufacturer.

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E-TDA7590

E-TDA7590

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