E-TDA7590 Datasheet E-TDA7590, E-TDA7590TR | P31-P33

TDA7590 Appendix 1

31/42

; settings for the clock control register

; 321098765432109876543210

;INIT_PLL_CLKCTL EQU $018cc1

INIT_PLL_CLKCTL EQU %000000011000001011000001 ; $018cc1

; 0001 --- DSPDF =1 (actual = DSPDF+1=3)

; 00 ------- TESTSEL

; 1 --------- DCKSRC (0:XTI; 1:FVCO)

; 1 ---------- DACLKEN (1: enable CODEC clocks)

; 0000010 ----------- MFSDF =2 (actual =MFSDF+1 = 3 )

; 011 ------------------ SEL (000:128,001:256, 010:384, etc)

; 0 --------------------- DSP_XTI (0:vco/DSPDF; 1:xti)

; 0 ---------------------- DAC_SEL (0:vco/MFSDF; 1:ext_dac_clk)

; 0 ----------------------- XTLD (0:Enabled; 1:Disabled)

ENDIF ; Settings per sci 115200

;------------------------------------------------------------------------

; Timer Intitialisation values

;------------------------------------------------------------------------

;--- TCSR0 --------------------------------------------------------------------

; settings for the Timer Control/Status Register

; 321098765432109876543210

INIT_TCSR0 EQU %000000001000101000000100 ; $8A04 mode0 / trm=1 / tce=1 / pce=1/ dir=out

INIT_TCSR1 EQU %000000001000101000000100 ; $8A04 mode0 / trm=1 / tce=1 / pce=1/ dir=out

INIT_TCSR2 EQU %000000001000101000000100 ; $8A04 mode0 / trm=1 / tce=1 / pce=1/ dir=out

; xx ----------------------->[23-22]; unused

; 0 ---------------------->[21] TCF ; Timer Compare Flag

; 0 --------------------->[20] TOF ; Timer Overflow Flag

; xxxx ----------------->[19-16] ; unused

; 0 ---------------->[15] PCE ; Prescaler Clock Enable

; x --------------->[14] ; unused

; 0 -------------->[13] DO ; Data Output

; 0 ------------->[12] DI ; Data Input

; 1 ------------>[11] DIR ; Direction

; x ----------->[10] ; unused

; 1 ---------->[ 9] TRM ; Timer Reload Mode

; 0 --------->[ 8] INV ; Inverter

; 0000 ----->[7-4] Tc[3-0] ; Timer Control = Mode0

; x ---->[ 3] ; unused

; 1 --->[ 2] TCIE ; Timer Compare Interrupt Enable

; 0 -->[ 1] TOIE ; Timer Overflow Enable

; 0 ->[ 0] TE ; Timer Enable

;--- TLR0 --------------------------------------------------------------------

; settings for the Timer Load Register

INIT_TLR0 EQU $000000

INIT_TLR1 EQU $000000

INIT_TLR2 EQU $000000

;--- TCPR0 --------------------------------------------------------------------

; settings for the Timer Compare Register

;INIT_TCPR0 EQU $000002

;INIT_TCPR1 EQU $000004

;INIT_TCPR2 EQU $000008

INIT_TCPR0 EQU $000000

INIT_TCPR1 EQU $000000

Appendix 1 TDA7590

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INIT_TCPR2 EQU $000000

;--- TPLR --------------------------------------------------------------------

; settings for the clock control register

; 321098765432109876543210

;INIT_TPLR EQU %001000000000001111100111 ; $2003E7 source TIO0 / divider = 999+1

INIT_TPLR EQU %000000000000001111100111 ; $0003E7 source internal / prescaler 999

; x------------------------> ; Reserved. Write to zero for future compatibility.

; 01----------------------> PS[1-0] ; Prescaler Source [00 internal / 01 external TIO0 /

; ; 10 external TIO0 / 11 external TIO0]

; 000000000010000000000-> PL[20-0] ; Prescaler Preload Value200400

;-------------------------------------------------------------------------------

; Interrupt Initialisation Values

;-------------------------------------------------------------------------------

; settings for the Interrupt priority register - Core

; 321098765432109876543210

INIT_IPR_C EQU %000000000000000000000000 ; $000000

; settings for the Interrupt priority register - peripherals

; 321098765432109876543210

INIT_IPR_P EQU %000000000011111001000100 ; $29C4 glitch sull'uscita del dac

; 00---- HI

; 11------ ESSI0

; 00-------- ESSI1

; 11---------- SCI

; 11------------ TIMER

; 11 ------------- SAI

; 11 --------------- CODEC

; 00 ----------------- PLL

; 00 ------------------- Unknow

; 00 --------------------- I2C

; 00 ----------------------- SPI

; 00 ------------------------- EMI

;-------------------------------------------------------------------------------

; Expansion Port Intitialisation values

;-------------------------------------------------------------------------------

;--- INIT_AAR0 -----------------------------------------------------------------------

; settings for the Address Attribute Register1

; 321098765432109876543210

INIT_AAR0 EQU %110000000000010000010000 ; C00410

; 00 --- BAT (00: Synchronous SRAM; 01: SRAM; 10: DRAM; 11: Reserved)

; 0 ----- BAAP (0:AA1 active low; 1: AA1 active high)

; 0 ------ BPEN (0: P space disabled; 1: P space enabled)

; 1 ------- BXEN (0: X data space disabled; 1: X data space enabled)

; 0 -------- BYEN (0: Y data space disabled; 1: Y data space enabled)

; 0 --------- BAM (0: 8 LSB of address will appear on A0-A7;

; 1: 8 LSB of address will appear on A16-A23)

; 0 ---------- BPAC (0: packing disabled; 1: packing enabled)

; 0100 ----------- BNC (Number of bits to compare; 1111, 1110, 1101 reserved)

; 110000000000 --------------- BAC (Address to compare; BNC most significant)

;--- INIT_BCR -----------------------------------------------------------------------

TDA7590 Appendix 1

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; settings for the Bus Control Register

; 321098765432109876543210

INIT_BCR EQU %001100000010010000100001 ; 306E10

;INIT_BCR EQU %000001111111110011100111 ; 30FE07

; 00111 --- BA0W (Area 0 wait states)

; 00000 -------- BA1W (Area 1 wait states)

; 111 ------------- BA2W (Area 2 wait states)

; 111 ---------------- BA3W (Area 3 wait states)

; 00000 ------------------- BDFW (Default area wait states)

; 0 ------------------------ BBS (0: ; 1: DSP is bus master READ ONLY)

; 0 ------------------------- BLH (0: ; 1: BLN always asserted)

; 0 -------------------------- BRH (0: ; 1: BRN always asserted)

;*******************************************************************************

; definitions addded by Paul Cassidy for salieri testbench

TRIGGER_TUBE EQU $12002

M_BCR EQU $FFFFFB ; Bus Control Register

M_AAR0 EQU $FFFFF9 ; Address Attribute 0

M_AAR1 EQU $FFFFF8 ; Address Attribute 1

M_AAR2 EQU $FFFFF7 ; Address Attribute 2

M_AAR3 EQU $FFFFF6 ; Address Attribute 3

;*******************************************************************************

;************************** Main Prog Starts Here ******************************

;*******************************************************************************

startp

org p:$0

jmp start

sci_int

org p:SCI_REC ; Interrupt SCI receive

jsr INT_SCIR

org p:SCI_TRANS ; Interrupt SCI transmit

jsr INT_SCIT

org p:SCI_REC_E ; Interrupt SCI framing error

jsr INT_SCIE

sai_int

org p:SAI_RDR

jsr INT_RDR

org p:SAI_TDE

jsr INT_TDE

org p:SAI_ROF

jsr INT_ROF

org p:SAI_TUF

jsr INT_TUF

essi_int

org p:essi0_rdf

jsr Comp_0

nop

org p:essi0_roe

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42

E-TDA7590

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Manufacturer:

STMicroelectronics

Description:

Digital Signal Processors & Controllers - DSP, DSC Digital signal IC speech and audio

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E-TDA7590

E-TDA7590

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