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E-TDA7590

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
Appendix 1 TDA7590
34/42
movep x:M_SSISR0,a0
movep x:M_RX0,y:(r0)+
org p:essi0_rls
nop
nop
org p:essi0_tde
jsr clr_tde0
nop
org p:essi0_tue
jsr clr_tue0
nop
org p:essi0_tls
nop
nop
timer_int
org p:Timer0_tcf
jsr INT_TMR0_tcf
org p:Timer0_tof
jsr INT_TMR0_tof
org p:Timer1_tcf
jsr INT_TMR1_tcf
org p:Timer1_tof
jsr INT_TMR1_tof
org p:Timer2_tcf
jsr INT_TMR2_tcf
org p:Timer2_tof
jsr INT_TMR2_tof
org x:0
states dsm ntaps
org y:0
coef dc .1,.3,-.1,.2
org p:$100
start
; setup external memory for sync with testbench
;------------------------------------------------------------------------
; Initialise Core
;------------------------------------------------------------------------
clr a
clr b
move #$0,r0
move #$fff,m0
ori #$3,mr ; mask interrupts
movep #INIT_IPR_C,x:IPR_C ; set CORE interrupt priorities
movep #INIT_IPR_P,x:IPR_P ; set PERIPHERAL interrupt priorities
;------------------------------------------------------------------------
; Initialise PLL
;------------------------------------------------------------------------
init_pll
movep #INIT_PLL_CSR,x:PLL_CSR ; enable the pll.
jclr #LOCK,x:<<PLL_CSR,* ; wait for lock.
TDA7590 Appendix 1
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movep #INIT_PLL_FCR,x:PLL_FCR ; set fract value.
bset #FRACEN,x:<<PLL_CSR ; enable fractional-n operation.
movep #INIT_PLL_CLKCTL,x:PLL_CLKCTL ; setup the clock generation.
IF 1
;------------------------------------------------------------------------
; Initialise CODEC
;------------------------------------------------------------------------
init_codec
movep #INIT_CODEC_CSR,x:CODEC_CSR ; initialise CODEC control/status reg
;------------------------------------------------------------------------
; Initialise SAI
;------------------------------------------------------------------------
; The receiver and transmitter control/status register are configured the same for simplicity only.
; Master mode , 24-bit word-size , MSB first , Low word clock = left word , Neg bit-clk polarity ,
; Non i2s format , (For 32-bit words) First bit x 8 , Interrupts enabled.
init_sai
movep #INIT_SAI_TCS,y:SAI_TCS ; initialise transmit control/status reg
movep #INIT_SAI_RCS,y:SAI_RCS ; initialise receiver control/status reg
;------------------------------------------------------------------------
; Enable gpios for HI
;------------------------------------------------------------------------
bset #GPIO0_DIR,x:GPIOCTRL ; Setup HI pin for GPIO mode
bset #GPIO0_DIR,x:GPIODIR ; Setup GPIO as output
bset #GPIO1_DIR,x:GPIOCTRL ; Setup HI pin for GPIO mode
bset #GPIO1_DIR,x:GPIODIR ; Setup GPIO as output
ENDIF
;------------------------------------------------------------------------
; Initialize ESSI0
;------------------------------------------------------------------------
IF 1
init_essi
movep #$181801,x:M_CRA0 ; cra0_addr, 24'b010110000001100000011110
; The divider control is set to 1 (2 words per frame)
; for Normal mode, bits are left aligned to bit 23. Word
; length is set to 24 bits.PM = 1 -> Fcore/4.
movep #$fc113e,x:M_CRB0 ; crb0_addr, 24'b111111000001010100111110
; The receive exception and transmit exception interrupts
; are enabled as are receive last slot and transmit last
; slot. It is set in the synchronous normal mode. Data and
; frame sync are clocked out on the rising edge of the clock.
; Frame sync polarity is positive and occurs together with the
; the first bit of data from the first slot. MSB is shifted
; first. SC2 o/p SC1 o/p SC0 o/p
Enable_pins
;------------------------------------------------------------------------
move #$01c000,x0 ;
movep x:M_CRB0,b1 ;
or x0,b1 ; // Enable TX2/TX1/TX0 (ESSI 0)
movep #$00003f,x:M_PCRC ; // ALL Pins are ESSI.
; check that all pins are enabled
rep #$05
nop
Appendix 1 TDA7590
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movep b1,x:M_CRB0
ENDIF
IF 1
;------------------------------------------------------------------------
; Enable gpios for TIMER
;------------------------------------------------------------------------
init_gpio
; movep #$000000,x:<<PCRC ; ESSI0 port as GPIO
; movep #$0000ff,x:<<PRRC ; ESSI0 port as OUT
Movep #$000000,x:<<PCRD ; ESSI1 port as GPIO
Movep #$000000,x:<<PRRD ; ESSI1 port as TIMER(INPUT)
;------------------------------------------------------------------------
; Initialise Timer
;------------------------------------------------------------------------
init_timer
bclr #0,x:M_TCSR0 ; Disable Timer0
bclr #0,x:M_TCSR1 ; Disable Timer1
bclr #0,x:M_TCSR2 ; Disable Timer2
movep #INIT_TCSR0,x:<<M_TCSR0 ; Timer0 enable at mode 0 + reload
movep #INIT_TPLR,x:<<M_TPLR ; Initial value of the timer counter
movep #INIT_TLR0,x:<<M_TLR0 ; Initial value of the timer counter
movep #INIT_TCPR0,x:<<M_TCPR0 ; Number of CLK/2 cycles until a trigger is generated
movep #INIT_TCSR1,x:<<M_TCSR1 ; Timer1 enable at mode 0 + reload
movep #INIT_TPLR,x:<<M_TPLR ; Initial value of the timer counter
movep #INIT_TLR1,x:<<M_TLR1 ; Initial value of the timer counter
movep #INIT_TCPR1,x:<<M_TCPR1 ; Number of CLK/2 cycles until a trigger is generated
movep #INIT_TCSR2,x:<<M_TCSR2 ; Timer2 enable at mode 0 + reload
movep #INIT_TPLR,x:<<M_TPLR ; Initial value of the timer counter
movep #INIT_TLR2,x:<<M_TLR2 ; Initial value of the timer counter
movep #INIT_TCPR2,x:<<M_TCPR2 ; Number of CLK/2 cycles until a trigger is generated
;------------------------------------------------------------------------
; Initialise Expansion Port and Flex Memory
;------------------------------------------------------------------------
init_expport
movep #INIT_AAR0,x:EXP_AAR0 ; initialise AAR0 control/status reg
movep #INIT_BCR,x:EXP_BCR ; initialise BCR reg
ENDIF
;------------------------------------------------------------------------
; Initialise SCI
;------------------------------------------------------------------------
IF 1
init_sci
movep #$E,x:SCCR_ADR
movep #$7,x:PCRE_ADR
movep #$11b02,x:SCR_ADR
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42

E-TDA7590

Mfr. #:
Buy E-TDA7590
Manufacturer:
STMicroelectronics
Description:
Digital Signal Processors & Controllers - DSP, DSC Digital signal IC speech and audio
Lifecycle:
New from this manufacturer.
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