MDK-2-GEVK Datasheet MDK-2-GEVK | P13-P15

AX8052F100

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The AX8052 uses P or Code Space to access its program.

Code space may also be read using the MOVC instruction.

Smaller amounts of data can be placed in the Internal (see

Note) or Data Space. A distinction is made in the upper half

of the Data Space between direct accesses (MOV reg,addr;

MOV addr,reg) and indirect accesses (MOV reg,@Ri;

MOV @Ri,reg; PUSH; POP); Direct accesses are routed to

the Special Function Registers, while indirect accesses are

routed to the internal RAM.

NOTE: The origin of Internal versus External (X) Space

is historical. External Space used to be outside

of the chip on the original 8052

Microcontrollers.

Large amounts of data can be placed in the External or X

Space. It can be accessed using the MOVX instructions.

Special Function Registers, as well as additional

Microcontroller Registers (XREG) and the Radio Registers

(RREG) are also mapped into the X Space.

Detailed documentation of the Special Function Registers

(SFR) and additional Microcontroller Registers can be

found in the AX8052 Programming Manual.

The Radio Registers are documented in the Programming

Manual of the connected Radio chip. Register Addresses

given in the Radio chip’s Programming Manual are relative

to the beginning of RREG, i.e. 0x4000 must be added to

these addresses. If an AXRadio chip is connected, the

appropriate provided ax8052f1xx.h header file should be

used.

Normally, accessing Radio Registers through the RREG

address range is adequate. Since Radio Register accesses

have a higher latency than other AX8052 registers, the

AX8052 provides a method for non−blocking access to the

Radio Registers. Accessing the RREG (nb) address range

initiates a Radio Register access, but does not wait for its

completion. The details of mechanism is documented in the

Radio Interface section of the AX8052 Programming

Manual.

The FLASH memory is organized as 64 pages of 1 kBytes

each. Each page can be individually erased. The write word

size is 16 Bits. The last 1 kByte page is dedicated to factory

calibration data and should not be overwritten.

Power Management

The microcontroller supports the following power modes:

Table 12. POWER MANAGEMENT

PCON

Name Description

00 RUNNING The microcontroller and all peripherals are running. Current consumption depends on the system clock

frequency and the enabled peripherals and their clock frequency.

01 STANDBY The microcontroller is stopped. All register and memory contents are retained. All peripherals continue to

function normally. Current consumption is determined by the enabled peripherals. STANDBY is exited

when any of the enabled interrupts become active.

10 SLEEP The microcontroller and its peripherals, except GPIO and the system controller, are shut down. Their

Software can determine individually for both blocks whether contents of that block are to be retained or

lost. SLEEP can be exited by any of the enabled GPIO or system controller interrupts. For most

applications this will be a GPIO or wakeup timer interrupt.

11 DEEPSLEEP The microcontroller, all peripherals and the transceiver are shut down. Only 4 bytes of scratch RAM are

retained. DEEPSLEEP can only be exited by tying the PB3 pin low.

AX8052F100

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Clocking

Figure 6. Clock System Diagram

LPOSC

Calib

FRCOSC

Calib

Wakeup

Timer

WDT

Clock

Monitor

Prescaler

÷1,2,4,...

FRCOSC

XOSC

LPXOSC

LPOSC

Interrupt

Internal Reset

RSYSCLK

Glitch Free Clock Switch

System Clock

The system clock can be derived from any of the following

clock sources:

• The crystal oscillator

• The low speed crystal oscillator

• The internal high speed RC (20 MHz) oscillator

• The internal low power (640 Hz/10 kHz) oscillator

An additional pre−scaler allows the selected oscillator to

be divided by a power of two. After reset, the

microcontroller starts with the internal high speed RC

oscillator selected and divided by two. I.e. at start−up, the

microcontroller runs with 10 MHz ± 10%. Clocks may be

switched any time by writing to the CLKCON register. In

order to prevent clock glitches, the switching takes

approximately 2·(T

), where T

and T

are the periods

of the old and the new clock. Switching may take longer if

the new oscillator first has to start up. Internal oscillators

start up instantaneously, but crystal oscillators may take a

considerable amount of time to start the oscillation.

CLKSTAT can be read to determine the clock switching

status.

A programmable clock monitor resets the CLKCON

a programmable time interval, thus reverts to the internal RC

oscillator.

Both internal oscillators can be slaved to one of the crystal

oscillators to increase the accuracy of the oscillation

frequency. While the reference oscillator runs, the internal

oscillator is slaved to the reference frequency by a digital

frequency locked loop. When the reference oscillator is

switched off, the internal oscillator continues to run

unslaved with the last frequency setting.

Reset and Interrupts

After reset, the microcontroller starts executing at address

0x0000. All registers except SCRATCH0...SCRATCH3 are

set to default values. RAM is either retained (SLEEP mode)

or undefined.

Several events can lead to resetting the microcontroller

core:

• POR or hardware RESET_N pin activated and released

• Leaving SLEEP or DEEPSLEEP mode

• Watchdog Reset

• Software Reset

The reset cause can be determined by reading the PCON

After POR or reset all registers are set to their default

values.

AX8052F100 has an integrated power−on−reset block

which is edge sensitive to VDD_IO. For many common

AX8052F100

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application cases no external reset circuitry is required.

However, if VDD_IO ramps cannot be guaranteed, an

external reset circuit is recommended. For detailed

recommendations and requirements see the AX8052

Application Note: Power On Reset.

The RESET_N pin contains a weak pull−up. However, it

is strongly recommended to connect the RESET_N pin to

VDD_IO if not used, for additional robustness.

The microcontroller supports 22 interrupt sources. Each

interrupt can be individually enabled and can be

programmed to have one of two possible priorities. The

interrupt vectors are located at 0x0003, 0x000B,…,

0x00AB.

Debugging

A hardware debug unit considerably eases debugging

compared to other 8052 microcontrollers. It allows to

reliably stop the micro−controller at breakpoints even if the

stack is smashed. The debug unit communicates with the

host PC running the debugger using a 3 wire interface. One

wire is dedicated (DBG_EN), while two wires are shared

with GPIO pins (PB6, PB7). When DBG_EN is driven high,

PB6 and PB7 convert to debug interface pins and the GPIO

functionality is no longer available. A pin emulation feature

however allows bits PINB[7:6] to be set and PORTB[7:6]

and DIRB[7:6] to be read by the debugger software. This

allows for example switches or LEDs connected to the PB6,

PB7 pins to be emulated in the debugger software whenever

the debugger is active.

In order to protect the intellectual property of the firmware

developer, the debug interface can be locked using a

developer−selectable 64−bit key. The debug interface is then

disabled and can only be enabled with the knowledge of this

64−bit key. Therefore, unauthorized persons cannot read the

firmware through the debug interface, but debugging is still

possible for authorized persons. Secure erase can be initiated

without key knowledge; secure erase ensures that the main

FLASH array is completely erased before erasing the key,

reverting the chip into factory state.

The DebugLink peripheral looks like an UART to the

microcontroller, and allows exchange of data between the

microcontroller and the host PC without disrupting program

execution.

Timer, Output Compare and Input Capture

The AX8052F100 features three general purpose 16−bit

timers. Each timer can be clocked by the system clock, any

of the available oscillators, or a dedicated input pin. The

timers also feature a programmable clock inversion, a

programmable prescaler that can divide by powers of two,

and an optional clock synchronization logic that

synchronizes the clock to the system clock. All three

counters are identical and feature four different counting

modes, as well as a SD mode that can be used to output an

analog value on a dedicated digital pin only employing a

simple RC lowpass filter.

Two output compare units work in conjunction with one

of the timers to generate PWM signals.

Two input capture units work in conjunction with one of

the timers to measure transitions on an input signal.

For software timekeeping, two additional 16−bit wakeup

timers with 4 16−bit event registers are provided, generating

an interrupt on match events.

UART

The AX8052F100 features two universal asynchronous

receiver transmitters. They use one of the timers as baud rate

generator. Word length can be programmed from 5 to 9 bits.

Dedicated Radio SPI Master Controller

The AX8052F100 features a dedicated Radio master SPI

controller. It is compatible with AX RF chips as well as some

third party SPI slave devices. It features efficient access by

the CPU. RF IC registers are mapped into the CPU X address

space.

SPI Master/Slave Controller

The AX8052F100 features a master/slave SPI controller.

Both 3 and 4 wire SPI variants are supported. In master

mode, any of the on−chip oscillators or the system clock may

be selected as clock source. An additional pre−scaler with

divide by two capability provides additional clocking

flexibility. Shift direction, as well as clock phase and

inversion, are programmable.

ADC, Analog Comparators and Temperature Sensor

The AX8052F100 features a 10−bit, 500 kSample/s

Analog to Digital converter. Figure 7 shows the block

diagram of the ADC. The ADC supports both single ended

and differential measurements. It uses an internal reference

of 1 V. ×1, ×10 and ×0.1 gain modes are provided. The ADC

may digitize signals on PA0…PA7, as well as VDD_IO and

an internal temperature sensor. The user can define four

channels which are then converted sequentially and stored

in four separate result registers. Each channel configuration

consists of the multiplexer and the gain setting.

The AX8052F100 contains an on−chip temperature

sensor. Built−in calibration logic allows the temperature

sensor to be calibrated in °C, °F or any other user defined

temperature scale.

The AX8052F100 also features two analog comparators.

Each comparator can either compare two voltages on

dedicated PA pins, or one voltage against the internal 1 V

reference. The comparator output can be routed to a

dedicated digital output pin or can be read by software. The

comparators are clocked with the system clock.

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