AX8052F100
www.onsemi.com
4
Table 1. PIN FUNCTION DESCRIPTIONS
Symbol Pin(s) Type Description
PR5 1 I/O/PU General Purpose I/O
VDD_CORE 2 P Regulated output voltage
PR4 3 I/O/PU General Purpose I/O
PR3 4 I/O/PU General Purpose I/O
PR2 5 I/O/PU General Purpose I/O
PR1 6 I/O/PU General Purpose I/O
PR0 7 I/O/PU General Purpose I/O
PC3 8 I/O/PU General Purpose I/O
PC2 9 I/O/PU General Purpose I/O
PC1 10 I/O/PU General Purpose I/O
PC0 11 I/O/PU General Purpose I/O
PB0 12 I/O/PU General Purpose I/O
PB1 13 I/O/PU General Purpose I/O
PB2 14 I/O/PU General Purpose I/O
PB3 15 I/O/PU General Purpose I/O
PB4 16 I/O/PU General Purpose I/O
PB5 17 I/O/PU General Purpose I/O
PB6, DBG_DATA 18 I/O/PU General Purpose I/O, debugger data line
PB7, DBG_CLK 19 I/O/PU General Purpose I/O, debugger clock line
DBG_EN 20 I/PD In−Circuit Debugger Enable
RESET_N 21 I/PU Optional reset pin. If this pin is not used it must be connected to VDD_IO
VDD_IO 22 P Unregulated power supply
PA0 23 I/O/PU General Purpose I/O
PA1 24 I/O/PU General Purpose I/O
PA2 25 I/O/PU General Purpose I/O
PA3 26 I/O/PU General Purpose I/O
PA4 27 I/O/PU General Purpose I/O
PA5 28 I/O/PU General Purpose I/O
GND Center pad P Ground on center pad of QFN, must be connected
A = analog input
I = digital input signal
O = digital output signal
PU = pull−up
I/O = digital input/output signal
N = not to be connected
P = power or ground
PD = pull−down
All digital inputs are Schmitt trigger inputs, digital input
and output levels are LVCMOS/LVTTL compatible. Port A
Pins (PA0 − PA7) must not be driven above VDD_IO, all
other digital inputs are 5 V tolerant. Pull−ups are
programmable for all GPIO pins.
