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ADUM4151ARIZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
5 kV, 7-Channel,
SPIsolator Digital Isolators for SPI
Data Sheet
ADuM4151/ADuM4152/ADuM4153
FEATURES
Supports up to 17 MHz SPI clock speed
4 high speed, low propagation delay, SPI signal isolation
channels
Three 250 kbps data channels
20-lead SOIC_IC package with 8.3 mm creepage
High temperature operation: 125°C
High common-mode transient immunity: >25 kV/µs
Safety and regulatory approvals
UL recognition per UL 1577
5000 V rms for 1 minute SOIC long package
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
Maximum working insulation voltage (V
IORM
): 849 V peak
APPLICATIONS
Industrial programmable logic controllers (PLCs)
Sensor isolation
GENERAL DESCRIPTION
The ADuM4151/ADuM4152/ADuM4153
1
are 7-channel,
SPIsolator™ digital isolators optimized for isolated serial peripheral
interfaces (SPIs). Based on the Analog Devices, Inc., iCoupler®
chip scale transformer technology, the low propagation delay in
the CLK, MO/SI, MI/SO, and
SS
SPI bus signals supports SPI
clock rates of up to 17 MHz. These channels operate with 14 ns
propagation delay and 1 ns jitter to optimize timing for SPI.
The ADuM4151/ADuM4152/ADuM4153 isolators also provide
three additional independent low data rate isolation channels in
three different channel direction combinations. Data in the slow
channels is sampled and serialized for a 250 kbps data rate with
up to 2.5 µs of jitter in the low speed channels.
FUNCTIONAL BLOCK DIAGRAMS
ENCODE
CONTROL
BLOCK
DECODE
DECODE ENCODE
ENCODE DECODE
ENCODE
DECODE
V
DD1
GND
1
MCLK
MO
MI
MSS
V
IA
V
IB
V
OC
V
DD2
GND
2
SCLK
SI
SO
SSS
V
OA
V
OB
V
IC
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
GND
1
GND
2
9
10
12
11
ADuM4151
CONTROL
BLOCK
12370-001
Figure 1. ADuM4151 Functional Block Diagram
ENCODE
DECODE
DECODE
ENCODE
ENCODE
DECODE
ENCODE
DECODE
V
DD1
GND
1
MCLK
MO
MI
MSS
V
IA
V
OB
V
OC
V
DD2
GND
2
SCLK
SI
SO
SSS
V
OA
V
IB
V
IC
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
GND
1
GND
2
9
10
12
11
ADuM4152
CONTROL
BLOCK
CONTROL
BLOCK
12370-002
Figure 2. ADuM4152 Functional Block Diagram
ENCODE
DECODE
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
V
DD1
GND
1
MCLK
MO
MI
MSS
V
OA
V
OB
V
OC
V
DD2
GND
2
SCLK
SI
SO
SSS
V
I
A
V
IB
V
IC
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
GND
1
GND
2
9
10
12
11
ADuM4153
CONTROL
BLOCK
CONTROL
BLOCK
12370-003
Figure 3. ADuM4153 Functional Block Diagram
1
Protected by U.S. Patents 5,952,849; 6,873,065; 6,262,600; and 7,075,329. Other patents are pending.
Rev. A
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
ADuM4151/ADuM4152/ADuM4153 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3.3 V Operation ............................ 5
Electrical Characteristics—Mixed 5 V/3.3 V Operation ........ 7
Electrical Characteristics—Mixed 3.3 V/5 V Operation ........ 9
Package Characteristics ............................................................. 10
Regulatory Information ............................................................. 11
Insulation and Safety Related Specifications .......................... 11
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
Insulation Characteristics .......................................................... 12
Recommended Operating Conditions .................................... 12
Absolute Maximum Ratings ......................................................... 13
ESD Caution................................................................................ 13
Pin Configurations and Function Descriptions ......................... 14
Typical Performance Characteristics ........................................... 17
Applications Information .............................................................. 18
Introduction ................................................................................ 18
Printed Circuit Board (PCB) Layout ....................................... 19
Propagation Delay Related Parameters ................................... 19
DC Correctness and Magnetic Field Immunity ..................... 19
Power Consumption .................................................................. 20
Insulation Lifetime ..................................................................... 20
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
3/15—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Table 2 ............................................................................ 3
Changes to Table 5 ............................................................................ 5
Changes to Table 8 ............................................................................ 7
Changes to Table 11 .......................................................................... 9
Changes to Table 14 ........................................................................ 11
Changes to Table 16 ........................................................................ 12
Changes to High Speed Channels Section .................................. 18
10/14—Revision 0: Initial Version
Rev. A | Page 2 of 22
Data Sheet ADuM4151/ADuM4152/ADuM4153
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at T
A
= 25°C and V
DD1
= V
DD2
= 5 V. Minimum and maximum specifications apply over the entire
recommended operation range: 4.5 V ≤ V
DD1
≤ 5.5 V, 4.5 V ≤ V
DD2
≤ 5.5 V, and −40°C ≤ T
A
≤ +125°C, unless otherwise noted. Switching
specifications are tested with C
L
= 15 pF and CMOS signal levels, unless otherwise noted.
Table 1. Switching Specifications
Parameter Symbol
A Grade
B Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
MCLK, MO, SO
SPI Clock Rate SPI
MCLK
1 17 MHz
Data Rate Fast (MO, SO) DR
FAST
2 34 Mbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
25 12 14 ns 50% input to 50% output
Pulse Width PW 100 12.5 ns Within PWD limit
Pulse Width Distortion PWD 3 2 ns |t
PLH
− t
PHL
|
Codirectional Channel Matching
1
t
PSKCD
3 2 ns
Jitter, High Speed J
HS
1 1 ns
MSS
Data Rate Fast DR
FAST
2 34 Mbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
21 25 21 25 ns 50% input to 50% output
Pulse Width PW 100 12.5 ns Within PWD limit
Pulse Width Distortion PWD 3 3 ns |t
PLH
− t
PHL
|
Setup Time
2
MSS
SETUP
1.5 10 ns
Jitter, High Speed J
HS
1 1 ns
V
IA
, V
IB
, V
IC
Data Rate Slow
DR
SLOW
250
250
kbps
Within PWD limit
Propagation Delay t
PHL
, t
PLH
0.1 2.6 0.1 2.6 µs 50% input to 50% output
Pulse Width PW 4 4 µs Within PWD limit
Jitter, Low Speed J
LS
2.5 2.5 µs
V
Ix
3
Minimum Input Skew
4
t
VIx SKEW
3
10 10 ns
1
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
2
The
MSS
signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that
MSS
reaches the output
ahead of another fast signal, set up
MSS
prior to the competing signal by different times depending on speed grade.
3
V
Ix
= V
IA
, V
IB
, or V
IC
.
4
An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 t
VIx SKEW
time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Table 2. Supply Current
Device Number Symbol
1 MHz, A Grade 17 MHz, B Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
ADuM4151 I
DD1
4.0 8.5 14.0 22 mA C
L
= 0 pF, low speed channels
I
DD2
6.0 11 13.5 23 mA C
L
= 0 pF, low speed channels
ADuM4152
I
DD1
4.8
8.5
14.0
21.5
mA
C
L
= 0 pF, low speed channels
I
DD2
6.5 10.5 14.0 22.5 mA C
L
= 0 pF, low speed channels
ADuM4153 I
DD1
4.0 8.5 14.0 22 mA C
L
= 0 pF, low speed channels
I
DD2
6.0 10.5 13.3 21 mA C
L
= 0 pF, low speed channels
Rev. A | Page 3 of 22
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

ADUM4151ARIZ-RL

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Digital Isolators 7 Ch Isolator f or SPI Interface
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