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ADUM4151ARIZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
Data Sheet ADuM4151/ADuM4152/ADuM4153
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 18.
Parameter Rating
Storage Temperature (T
ST
) Range −65°C to +150°C
Ambient Operating Temperature (T
A
)
Range
−40°C to +125°C
Supply Voltages (V
DD1
, V
DD2
) −0.5 V to +7.0 V
Input Voltages (V
IA
, V
IB
, V
IC
, MCLK, MO,
SO,
MSS
)
−0.5 V to V
DDx
+ 0.5 V
Output Voltages (SCLK,
SSS
, MI, SI,
V
OA
, V
OB
, V
OC
)
−0.5 V to V
DDx
+ 0.5 V
Average Current per Output Pin
1
−10 mA to +10 mA
Common-Mode Transients
2
−100 kV/µs to +100 kV/µs
1
See Figure 4 for maximum safety rated current values across temperature.
2
Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum ratings may cause latch-up
or permanent damage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 19. Maximum Continuous Working Voltage
1
Parameter Value Constraint
60 Hz AC Voltage 400 V rms 20-year lifetime at
0.1% failure rate, zero
average voltage
DC Voltage 1173 V peak Limited by the
creepage of the
package,
Pollution Degree 2,
Material Group II
2, 3
1
See the Insulation Lifetime section for more details.
2
Other pollution degree and material group requirements yield a different limit.
3
Some system level standards allow components to use the printed wiring
board (PWB) creepage values. The supported dc voltage may be higher for
those standards.
ESD CAUTION
Rev. A | Page 13 of 22
ADuM4151/ADuM4152/ADuM4153 Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
DD1
1
GND
1
2
MCLK
3
MO
4
20
19
18
17
MI
5
MSS
6
V
IA
7
16
15
14
V
IB
8
13
V
OC
9
12
GND
1
V
DD2
GND
2
SCLK
SI
SO
SSS
V
OA
V
OB
V
IC
GND
2
10
11
ADuM4151
TOP VIEW
(Not to Scale)
12370-005
Figure 5. ADuM4151 Pin Configuration
Table 20. ADuM4151 Pin Function Descriptions
Pin No. Mnemonic Direction Description
1 V
DD1
Power Input Power Supply for Isolator Side 1. A bypass capacitor from V
DD1
to GND
1
to local ground is
required.
2, 10 GND
1
Return Ground 1. Ground reference for Isolator Side 1.
3
MCLK
Clock
SPI Clock from the Master Controller.
4 MO Input SPI Data from the Master to the Slave MO/SI Line.
5 MI Output SPI Data from the Slave to the Master MI/SO Line.
6
MSS
Input Slave Select from the Master. This signal uses an active low logic. The slave select pin requires a 10 ns
setup time from the next clock or data edge.
7 V
IA
Input Low Speed Data Input A.
8 V
IB
Input Low Speed Data Input B.
9 V
OC
Output Low Speed Data Output C.
11, 19 GND2 Return Ground 2. Ground reference for Isolator Side 2.
12 V
IC
Input Low Speed Data Input C.
13 V
OB
Output Low Speed Data Output B.
14
V
OA
Output
Low Speed Data Output A.
15
SSS
Output Slave Select to the Slave. This signal uses an active low logic.
16 SO Input SPI Data from the Slave to the Master MI/SO Line.
17 SI Output SPI Data from the Master to the Slave MO/SI Line.
18 SCLK Output SPI Clock from the Master Controller.
20 V
DD2
Power Input Power Supply for Isolator Side 2. A bypass capacitor from V
DD2
to GND
2
to local ground is
required.
Rev. A | Page 14 of 22
Data Sheet ADuM4151/ADuM4152/ADuM4153
V
DD1
1
GND
1
2
MCLK
3
MO
4
20
19
18
17
MI
5
MSS
6
V
IA
7
16
15
14
V
OB
8
13
V
OC
9
12
GND
1
V
DD2
GND
2
SCLK
SI
SO
SSS
V
OA
V
IB
V
IC
GND
2
10
11
ADuM4152
TOP VIEW
(Not to Scale)
12370-006
Figure 6. ADuM4152 Pin Configuration
Table 21. ADuM4152 Pin Function Descriptions
Pin No. Mnemonic
Direction Description
1 V
DD1
Power Input Power Supply for Isolator Side 1. A bypass capacitor from V
DD1
to GND
1
to local ground is required.
2, 10 GND
1
Return Ground 1. Ground reference for Isolator Side 1.
3 MCLK
Clock SPI Clock from the Master Controller.
4 MO Input SPI Data from the Master to the Slave MO/SI Line.
5 MI Output SPI Data from the Slave to the Master MI/SO Line.
6
MSS
Input Slave Select from the Master. This signal uses an active low logic. The slave select pin requires a 10 ns
setup time from the next clock or data edge.
7 V
IA
Input Low Speed Data Input A.
8 V
OB
Output Low Speed Data Output B.
9 V
OC
Output Low Speed Data Output C.
11, 19 GND
2
Return Ground 2. Ground reference for Isolator Side 2.
12 V
IC
Input Low Speed Data Input C.
13 V
IB
Input Low Speed Data Input B.
14 V
OA
Output Low Speed Data Output A.
15
SSS
Output
Slave Select to the Slave. This signal uses an active low logic.
16 SO Input SPI Data from the Slave to the Master MI/SO Line.
17 SI Output SPI Data from the Master to the Slave MO/SI Line.
18 SCLK Output SPI Clock from the Master Controller.
20 V
DD2
Power Input Power Supply for Isolator Side 2. A bypass capacitor from V
DD2
to GND
2
to local ground is required.
Rev. A | Page 15 of 22
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

ADUM4151ARIZ-RL

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Manufacturer:
Analog Devices Inc.
Description:
Digital Isolators 7 Ch Isolator f or SPI Interface
Lifecycle:
New from this manufacturer.
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