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ADUM4151ARIZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
ADuM4151/ADuM4152/ADuM4153 Data Sheet
Table 3. For All Models
1, 2, 3
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
MCLK,
MSS
, MO, SO, V
IA
, V
IB
, V
IC
Logic High Input Threshold V
IH
0.7 × V
DDx
V
Logic Low Input Threshold V
IL
0.3 × V
DDx
V
Input Hysteresis V
IHYST
500 mV
Input Current per Channel I
I
−1 +0.01 +1 µA 0 V ≤ V
INPUT
≤ V
DDx
SCLK,
SSS
, MI, SI, V
OA
, V
OB
, V
OC
Logic High Output Voltages V
OH
V
DDx
− 0.1 5.0 V I
OUTPUT
= −20 µA, V
INPUT
= V
IH
V
DDx
− 0.4
4.8
V
I
OUTPUT
= −4 mA, V
INPUT
= V
IH
Logic Low Output Voltages
V
OL
0.0
0.1
V
I
OUTPUT
= 20 µA, V
INPUT
= V
IL
0.2 0.4 V I
OUTPUT
= 4 mA, V
INPUT
= V
IL
V
DD1
, V
DD2
Undervoltage Lockout UVLO 2.6 V
Supply Current per High Speed Channel
Dynamic Input Supply Current I
DDI(D)
0.080 mA/Mbps
Dynamic Output Supply Current I
DDO(D)
0.046 mA/Mbps
Supply Current for All Low Speed Channels
Quiescent Side 1 Current I
DD1(Q)
4.3 mA
Quiescent Side 2 Current I
DD2Q)
6.1 mA
AC SPECIFICATIONS
Output Rise/Fall Time t
R
/t
F
2.5 ns 10% to 90%
Common-Mode Transient Immunity
4
|CM| 25 35 kV/µs V
INPUT
= V
DDx
, V
CM
= 1000 V,
transient magnitude = 800 V
1
V
DDx
= V
DD1
or V
DD2
.
2
V
INPUT
is the input voltage of any of the MCLK,
MSS
, MO, SO, V
IA
, V
IB
, or V
IC
pins.
3
I
OUTPUT
is the output current of any of the SCLK,
SSS
, MI, SI, V
OA
, V
OB
, or V
OC
pins.
4
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the V
OH
and V
OL
limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. A | Page 4 of 22
Data Sheet ADuM4151/ADuM4152/ADuM4153
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at T
A
= 25°C and V
DD1
= V
DD2
= 3.3 V. Minimum and maximum specifications apply over the entire
recommended operation range: 3.0 V ≤ V
DD1
≤ 3.6 V, 3.0 V ≤ V
DD2
≤ 3.6 V, and −40°C ≤ T
A
≤ +125°C, unless otherwise noted. Switching
specifications are tested with C
L
=15 pF and CMOS signal levels, unless otherwise noted.
Table 4. Switching Specifications
Parameter Symbol
A Grade B Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
MCLK, MO, SO
SPI Clock Rate SPI
MCLK
1 12.5 MHz
Data Rate Fast (MO, SO) DR
FAST
2 34 Mbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
30 20 ns 50% input to 50% output
Pulse Width PW 100 12.5 ns Within PWD limit
Pulse Width Distortion PWD 3 3 ns |t
PLH
− t
PHL
|
Codirectional Channel Matching
1
t
PSKCD
4 2 ns
Jitter, High Speed
J
HS
1
1
ns
MSS
Data Rate Fast DR
FAST
2 34 Mbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
30 30 ns 50% input to 50% output
Pulse Width PW 100 12.5 ns Within PWD limit
Pulse Width Distortion PWD 3 3 ns |t
PLH
− t
PHL
|
Setup Time
2
MSS
SETUP
1.5 10 ns
Jitter, Low Speed J
LS
2.5 2.5 ns
V
IA
, V
IB
, V
IC
Data Rate Slow DR
SLOW
250 250 kbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
0.1 2.6 0.1 2.6 µs 50% input to 50% output
Pulse Width PW 4 4 µs Within PWD limit
Jitter, Low Speed J
LS
2.5 2.5 µs |t
PLH
− t
PHL
|
V
Ix
3
Minimum Input Skew
4
t
VIx SKEW
3
10 10 ns
1
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
2
The
MSS
signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that
MSS
reaches the output
ahead of another fast signal, set up
MSS
prior to the competing signal by different times depending on speed grade.
3
V
Ix
= V
IA
, V
IB
, or V
IC
.
4
An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 t
VIx SKEW
time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Table 5. Supply Current
Device Number Symbol
1 MHz, A Grade/B Grade 17 MHz, B Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
ADuM4151 I
DD1
3.8 7 10.5 18 mA C
L
= 0 pF, low speed channels
I
DD2
5.1 8 9.0 17 mA C
L
= 0 pF, low speed channels
ADuM4152 I
DD1
3.7 6.5 11.7 18 mA C
L
= 0 pF, low speed channels
I
DD2
5.2 8 10.0 16 mA C
L
= 0 pF, low speed channels
ADuM4153 I
DD1
3.7 6.5 11.7 18 mA C
L
= 0 pF, low speed channels
I
DD2
5.2 9 10.0 15 mA C
L
= 0 pF, low speed channels
Rev. A | Page 5 of 22
ADuM4151/ADuM4152/ADuM4153 Data Sheet
Table 6. For All Models
1, 2, 3
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
MCLK,
MSS
, MO, SO, V
IA
, V
IB
, V
IC
Logic High Input Threshold V
IH
0.7 × V
DDx
V
Logic Low Input Threshold V
IL
0.3 × V
DDx
V
Input Hysteresis V
IHYST
500 mV
Input Current per Channel I
I
−1 +0.01 +1 µA 0 V ≤ V
INPUT
≤ V
DDx
SCLK,
SSS
, MI, SI, V
OA
, V
OB
, V
OC
Logic High Output Voltages V
OH
V
DDx
− 0.1 5.0 V I
OUTPUT
= −20 µA, V
INPUT
= V
IH
V
DDx
− 0.4
4.8
V
I
OUTPUT
= −4 mA, V
INPUT
= V
IH
Logic Low Output Voltages
V
OL
0.0
0.1
V
I
OUTPUT
= 20 µA, V
INPUT
= V
IL
0.2 0.4 V I
OUTPUT
= 4 mA, V
INPUT
= V
IL
V
DD1
, V
DD2
Undervoltage Lockout UVLO 2.6 V
Supply Current per High Speed Channel
Dynamic Input Supply Current I
DDI(D)
0.086 mA/Mbps
Dynamic Output Supply Current I
DDO(D)
0.019 mA/Mbps
Supply Current for All Low Speed Channels
Quiescent Side 1 Current I
DD1(Q)
2.9 mA
Quiescent Side 2 Current I
DD2Q)
4.7 mA
AC SPECIFICATIONS
Output Rise/Fall Time t
R
/t
F
2.5 ns 10% to 90%
Common-Mode Transient Immunity
4
|CM| 25 35 kV/µs V
INPUT
= V
DDx
, V
CM
= 1000 V,
transient magnitude = 800 V
1
V
DDx
= V
DD1
or V
DD2
.
2
V
INPUT
is the input voltage of any of the MCLK,
MSS
, MO, SO, V
IA
, V
IB
, or V
IC
pins.
3
I
OUTPUT
is the output current of any of the SCLK,
SSS
, MI, SI, V
OA
, V
OB
, or V
OC
pins.
4
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the V
OH
and V
OL
limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. A | Page 6 of 22
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ADUM4151ARIZ-RL

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Manufacturer:
Analog Devices Inc.
Description:
Digital Isolators 7 Ch Isolator f or SPI Interface
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