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M34F04-WMN6TP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
Device operation M34F04
10/26 DocID11090 Rev 4
3 Device operation
The device supports the I
2
C protocol. This is summarized in Figure 3. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The M24Cxx device is always a slave in all
communication.
3.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the High state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.
3.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and
driven High. A Stop condition terminates communication between the device and the bus
master. A Read command that is followed by NoAck can be followed by a Stop condition to
force the device into the Stand-by mode. A Stop condition at the end of a Write command
triggers the internal EEPROM Write cycle.
3.3 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9
th
clock pulse period, the receiver pulls Serial Data (SDA) Low to
acknowledge the receipt of the eight data bits.
3.4 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven Low.
DocID11090 Rev 4 11/26
M34F04 Device operation
25
3.5 Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the Device Select Code,
shown in Table 2 (on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device Type Identifier, and a 2-bit Chip Enable
“Address” (E2, E1). To address the memory array, the 4-bit Device Type Identifier is 1010b.
When the Device Select Code is received on Serial Data (SDA), the device only responds if
the Chip Enable Address is the same as the value on the Chip Enable (E1, E2) inputs.
The 8
th
bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9
th
bit time. If the device does not match
the Device Select code, it deselects itself from the bus, and goes into Stand-by mode.
Using the E1 and E2 inputs pins, up to four M34F04 devices can be connected to one I
2
C
bus.
Table 2. Device select code
Device Type Identifier
(1)
1. The most significant bit, b7, is sent first.
Chip Enable
(2)(3)
2. E1 and E2 are compared against the respective external pins on the memory device.
3. A8 represents most significant bits of the address.
RW
b7 b6 b5 b4 b3 b2 b1 b0
Device Select
Code
1010E2E1A8RW
Table 3. Operating modes
Mode RW bit WC
(1)
1. Z = unconnected and floating
X = VIH or VIL or unconnected and floating.
Bytes Initial Sequence
Current Address Read 1 X 1 START, Device Select, RW
= 1
Random Address Read
0X
1
START, Device Select, RW
= 0, Address
1 X reSTART, Device Select, RW
= 1
Sequential Read 1 X ≥ 1
Similar to Current or Random Address
Read
Byte Write (upper addresses) 0 V
IL
or Z 1 START, Device Select, RW = 0
Byte Write (lower addresses) 0 X 1 START, Device Select, RW
= 0
Page Write (upper addresses) 0 V
IL
or Z ≤ 16 START, Device Select, RW = 0
Page Write (lower addresses) 0 X ≤ 16 START, Device Select, RW
= 0
Device operation M34F04
12/26 DocID11090 Rev 4
Figure 4. Write mode sequences, to addresses in the top half, with WC=1 (data write
inhibited)
3.6 Write operations
Following a Start condition the bus master sends a Device Select Code with the RW bit
reset to 0. The device acknowledges this, as shown in Figure 5, and waits for an address
byte. The device responds to the address byte with an acknowledge bit, and then waits for
the data byte.
When the bus master generates a Stop condition immediately after the Ack bit (in the “10
th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal memory Write
cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write
cycle.
During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and
the device does not respond to any requests.
3.7 Byte write
After the Device Select code and the address byte, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC
) being driven High (during
the period from the Start condition until the end of the address byte), the device replies to
the data byte with NoAck, as shown in Figure 4, and the location is not modified. If, instead,
the addressed location is not Write-protected, the device replies with Ack. The bus master
terminates the transfer by generating a Stop condition, as shown in Figure 5.
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

M34F04-WMN6TP

Mfr. #:
Buy M34F04-WMN6TP
Manufacturer:
STMicroelectronics
Description:
EEPROM 4Kbit Serial EE
Lifecycle:
New from this manufacturer.
Delivery:
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