DocID11090 Rev 4 13/26
M34F04 Device operation
25
3.8 Page write
The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits are the same. If more bytes are sent than will fit up to the end of the
page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the
device if Write Control (WC
) is Low. If the addressed location is Write-protected, by Write
Control (WC
) being driven High (during the period from the Start condition until the end of
the address byte), the device replies to the data bytes with NoAck, as shown in Figure 4,
and the locations are not modified. After each byte is transferred, the internal byte address
counter (the 4 least significant address bits only) is incremented. The transfer is terminated
by the bus master generating a Stop condition.
Figure 5. Write mode sequences with WC
=0 (data write enabled)
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Device operation M34F04
14/26 DocID11090 Rev 4
Figure 6. Write cycle polling flowchart using ACK
3.9 Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (t
w
) is
shown in Table 9, but the typical time is shorter. To make use of this, a polling sequence can
be used by the bus master.
The sequence, as shown in Figure 6, is:
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a Device Select Code (the
first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
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DocID11090 Rev 4 15/26
M34F04 Device operation
25
Figure 7. Read mode sequences
Note: The seven most significant bits of the Device Select Code of a Random Read (in the 1
st
and
3
rd
bytes) must be identical.
3.10 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
3.11 Random address read
A dummy Write is performed to load the address into the address counter (as shown in
Figure 7) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the Device Select Code, with the RW
bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
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M34F04-WMN6TP

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
EEPROM 4Kbit Serial EE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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