Signal description M34F04
8/26 DocID11090 Rev 4
2 Signal description
2.1 Serial clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor can be connected from Serial Clock
(SCL) to V
CC
. (Figure 10 indicates how the value of the pull-up resistor can be calculated).
In most applications, though, this method of synchronization is not employed, and so the
pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than
open drain) output.
2.2 Serial data (SDA)
This bi-directional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to V
CC
. (Figure 10 indicates how
the value of the pull-up resistor can be calculated).
2.3 Chip enable (E1, E2)
These input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2) of the 7-bit Device Select Code. These inputs must be tied to V
CC
or
V
SS
, to establish the Device Select Code.
2.4 Write control (WC)
This input signal is useful for protecting half of the memory from inadvertent write
operations. Write operations are disabled to the upper half (1FFh to 100h) of the memory
array when Write Control (WC
) is driven High. When unconnected, the signal is internally
read as V
IL
, and Write operations are allowed.
When attempting to write in the upper half of the memory, while Write Control (WC) is being
driven High, Device Select and Address bytes are acknowledged, Data bytes are not
acknowledged.
