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IDT70824S25PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
6.42
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory Military and Commercial Temperature Ranges
19
Sequential Counter Enable Cycle After Reset, Write Cycle
(1,4,6)
Sequential Counter Enable Cycle After Reset, Read Cycle
(1,4)
NOTES:
1. 'D0' represents data input for Address = 0, 'D1' represents data input for Address = 1, etc.
2. If CNTEN = V
IL then 'D1' would be written into 'A1' at this point.
3. Data output is available at a t
CD after the SR/W = VIH is clocked. The RST sets SR/W = LOW internally and therefore disables the output until the next clock.
4. SCE = V
IL throughout all cycles.
5. If CNTEN=V
IL then 'D1' would be clocked out (read) at this point.
6. SR/W = V
IL.
RST
CNTEN
SCLK
(2)
D0
SI/O
IN
3099 drw 23
D1 D2 D3 D4
RST
CNTEN
SCLK
(5)
SI/O
OUT
3099 drw 24
D0
D2
D1
D3
SR/W
(3)
(5)
20
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory Military and Commercial Temperature Ranges
Random Access Port - Reset Timing
Random Access Port Restart Timing of Sequential Port
(1)
NOTES:
1. The sequential port is in the STOP mode and is being restarted from the random port by the Bit 4 Counter Release (see Case 5).
2. "0" is written to Bit 4 from the random port at address [A
2 - A0] = 100, when CMD = VIL and CE = VIH. The device is in the Buffer Command Mode (see Case 5).
3. CLR is an internal signal only and is shown for reference only.
4. Sequential port must also prohibit SR/W or SCE from being LOW for t
WERS and tRSRC periods or SCLK must not toggle from LOW-to-HIGH until after tRSRC.
t
RSPW
RST
R/W,SR/WCMD
or (UB + LB)
t
RSRC
t
WERS
EOB
(1 or 2)
Flag Valid
t
RSFV
3099 drw 25
(4)
t
FS
SCLK
R/W
(Internal Signal)
2-5ns
6-7ns
0.5 x t
CYC
3099 drw 26
CLR
Block
(3)
(2)
6.42
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory Military and Commercial Temperature Ranges
21
Ordering Information
NOTE:
1. Industrial temperature range is available on selected TQFP packages in standard power.
For specific speeds, packages and powers contact your sales office.
3099 drw 27
X
Power
XX
Speed
X
Package
X
Process/
Temperature
Range
Blank
I
(1)
B
Commercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)
Military (–55°C to +125°C)
Compliant to MIL-PRF-38535 QML
G
PF
84-pin PGA (G84-3)
80-pin TQFP (PN80-1)
20
25
35
45
S
L
Standard Power
Low Power
70824
Device
Type
64K (4K x 16) Sequential Access Random
Access Memory
70824
Speed in nanoseconds
Commercial Only
Commercial Only
Commercial & Military
Commercial & Military
,
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
3/8/99: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Page 2 Added additional notes to pin configurations
6/4/99: Changed drawing format
11/10/99: Replaced IDT logo
4/18/00: Page 3 Added "Outputs" in Sequential pin description table
Changed ±200mV to 0mV in notes
5/23/00: Page 4 Increased storage temperature parameter
Clarified TA parameter
Page 5 DC Electrical parameters–changed wording from "open" to "disabled"
01/29/09: Page 21 Removed "IDT" from orderable part number
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

IDT70824S25PF8

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Description:
IC RAM 64K PARALLEL 80TQFP
Lifecycle:
New from this manufacturer.
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