6.42
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory Military and Commercial Temperature Ranges
7
Truth Table II: Sequential Read
(1,2,3,6,8)
Truth Table I: Random Access Read and Write
(1,2)
Truth Table III: Sequential Write
(1,2,3,4,5,6,7,8)
NOTES:
1. H = V
IH, L = VIL, X = Don't Care, and HIGH-Z = High-impedance.
2. RST, SCE, CNTEN, SR/W, SLD, SSTRT
1, SSTRT2, SCLK, SI/O0-SI/O15, EOB1, EOB2, and SOE are unrelated to the random access port control and operation.
3. If OE = V
IL during write, tWHZ must be added to the tWP or tCW write pulse width to allow the bus to float prior to being driven.
4. Byte operations to control register using UB and LB separately are also allowed.
NOTES:
1. H = V
IH, L = VIL, X = Don't Care, and HIGH-Z = High-impedance. LOW = VOL.
2. RST, SLD, SSTRT
1, SSTRT2 are continuously HIGH during a sequential write access, other than pointer access operations.
3. CE, OE, R/W, CMD, LB, UB, and I/O
0-I/O15 are unrelated to the sequential port control and operation except for CMD which must not be used concurrently with the
sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = V
IH) during sequential port access.
4. SOE must be HIGH (SOE=V
IH) prior to write conditions only if the previous cycle is a read cycle, since the data being written must be an input at the rising edge
of the clock during the cycle in which SR/W = V
IL.
5. SI/O
IN refers to SI/O0-SI/O15 inputs.
6. "LAST" refers to the previous value still being output, no change.
7. Termination of a write is done on the LOW-to-HIGH transition of SCLK if SR/W or SCE is HIGH.
8. When CLKEN=LOW, the address is incremented on the next rising edge before any operation takes place. See the diagrams called "Sequential Counter Enable Cycle
after Reset, Read (and write) Cycle".
Inputs/Outputs
MODE
CE CMD
R/W
OE LB UB
I/O
0
-I/O
7
I/O
8-
I/O
15
LHHLLLDATA
OUT
DATA
OUT
Read both Bytes.
LHHLLHDATA
OUT
High-Z Read lower Byte only.
LHHLHLHigh-ZDATA
OUT
Read upper Byte only.
LHL H
(3)
LLDATA
IN
DATA
IN
Write to both Bytes.
LHL H
(3)
LHDATA
IN
High-Z Write to lower Byte only.
LHL H
(3)
H L High-Z DATA
IN
Write to upper Byte only.
H H X X X X High-Z High-Z Both Bytes deselected and powered down.
L H H H X X High-Z High-Z Outputs disabled but not powered down.
L H X X H H High-Z High-Z Both Bytes deselected but not powered down.
HLL H
(3)
L
(4)
L
(4 )
DATA
IN
DATA
IN
Write I/O
0
-I/O
11
to the Buffer Command Register.
HLHL
L
(4)
L
(4 )
DATA
OUT
DATA
OUT
Read contents of the Buffer Command Register
via I/O
0
-I/O
12
.
3099 tbl 11
Inputs/Outputs
MODESCLK
SCE CNT EN
SR/W
EOB
1
EOB
2
SOE
SI/O
↑
LLHLOWLASTL[EOB
1
] Counter Advanced Sequential Read with EOB
1
reached.
↑
L H H LAST LAST L [EOB
1 - 1
] Non-Counter Advanced Sequential Read, without EOB
1
reached
↑
LLHLASTLOWL[EOB
2
] Counter Advanced Sequential Read with EOB
2
reched.
↑
L H H LAST LAST L [EOB
2 - 1
] Non-Counter Advanced Sequential Read without EOB
2
reached
↑ L L H LOW LOW H High-Z Counter Advanced Sequential Non-Read with EOB
1
and EOB
2
reached
30 99 tbl 12
Inputs/Outputs
MODESCLK
SCE CNTEN
SR/W
EOB
1
EOB
2
SOE
SI/O
↑
L H L LAST LAST H SI/O
IN
Non-Counter Advanced Sequential Write, without EOB
1
or EOB
2
reached.
↑
LLLLOWLOWHSI/O
IN
Counter Advanced Sequential Write with EOB
1
and EOB
2
reached.
↑
H H X LAST LAST X High-Z No Write or Read due to Sequential port Deselect. No counter advance.
↑
H L X NEXT NEXT X High-Z No Write or Read due to Sequential port Deselect. Counter does advance.
30 99 tbl 13
