1. General description
The 74LVT16500A is a high-performance BiCMOS product designed for V
CC
operation at
3.3 V.
This device is an 18-bit universal transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock
(CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent
mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a
HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on
the HIGH-to-LOW transition of CPAB. When OEAB is HIGH, the outputs are active. When
OEAB is LOW, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The
output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW).
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
2. Features
n 18-bit bidirectional bus interface
n 3-state buffers
n Output capability: +64 mA and −32 mA
n TTL input and output switching levels
n Input and output interface capability to systems at 5 V supply
n Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
n Live insertion/extraction permitted
n Power-up reset
n Power-up 3-state
n No bus current loading when output is tied to 5 V bus
n Negative edge-triggered clock inputs
n Latch-up protection:
u JESD78: exceeds 500 mA
n ESD protection:
u MIL STD 883 Method 3015: exceeds 2000 V
u CDM JESD22-C101-C exceeds 1000 V
74LVT16500A
3.3 V 18-bit universal bus transceiver; 3-state
Rev. 03 — 29 May 2006 Product data sheet
