74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 29 May 2006 9 of 19
Philips Semiconductors
74LVT16500A
3.3 V 18-bit universal bus transceiver; 3-state
[1] Typical values are at V
CC
= 3.3 V and T
amb
= 25 °C.
[2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
[3] Unused pins at V
CC
or GND.
[4] This is the bus hold overdrive current required to force the input to the opposite logic state.
[5] This parameter is valid for any V
CC
between 0 V and 1.2 V with a transition time of up to 10 ms. From V
CC
= 1.2 V to V
CC
= 3.0 V ± 0.3 V
a transition time of 100 µs is permitted. This parameter is valid for T
amb
= 25 °C only.
[6] I
CC
is measured with outputs pulled to V
CC
or GND.
[7] This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND.
10. Dynamic characteristics
∆I
CC
additional quiescent supply
current
per input pin; V
CC
= 3 V to 3.6 V; one input
at V
CC
− 0.6 V; other inputs at V
CC
or GND
[7]
- 0.1 0.2 mA
C
i
input capacitance control pins; V
I
= 0 V or 3.0 V - 3 - pF
C
io
input/output capacitance I/O pins; V
I/O
= 0 V or 3.0 V - 9 - pF
Table 6. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol Parameter Conditions Min Typ Max Unit
V
CC
= 2.7 V; T
amb
= −40 °C to 85 °C
t
PLH
propagation delay
An to Bn or Bn to An see
Figure 5 - - 5.4 ns
CPAB to Bn or CPBA to An see Figure 6 - - 6.4 ns
LEAB to Bn or LEBA to An see
Figure 7 - - 6.4 ns
t
PHL
propagation delay
An to Bn or Bn to An see
Figure 5 - - 5.4 ns
CPAB to Bn or CPBA to An see Figure 6 - - 6.4 ns
LEAB to Bn or LEBA to An see
Figure 7 - - 6.4 ns
t
PZH
output enable time to HIGH-level see Figure 8 - - 5.5 ns
t
PZL
output enable time to LOW-level see Figure 9 - - 5.2 ns
t
PHZ
output disable time from HIGH-level see Figure 8 - - 6.3 ns
t
PLZ
output disable time from LOW-level see Figure 9 - - 5.6 ns
t
su(H)
setup time HIGH
An to
CPAB or Bn to CPBA see Figure 10 2.5 - - ns
An to LEAB with
CPAB LOW or
Bn to LEBA with
CPBA LOW
see
Figure 10 2.2 - - ns
An to LEAB with
CPAB HIGH or
Bn to LEBA with
CPBA HIGH
see
Figure 10 2.7 - - ns
