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74LVT16500ADGG,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 29 May 2006 3 of 19
Philips Semiconductors
74LVT16500A
3.3 V 18-bit universal bus transceiver; 3-state
Fig 3. Logic diagram
001aaf035
54A0
1D
C1
to 17 other channels
CLK
1D
B0
3
OEBA
27
CPBA
30
LEBA
28
LEAB
2
CPAB
55
OEAB
1
C1
CLK
74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 29 May 2006 4 of 19
Philips Semiconductors
74LVT16500A
3.3 V 18-bit universal bus transceiver; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 4. Pin configuration
74LVT16500A
OEAB GND
LEAB CPAB
A0 B0
GND GND
A1 B1
A2 B2
V
CC
V
CC
A3 B3
A4 B4
A5 B5
GND GND
A6 B6
A7 B7
A8 B8
A9 B9
A10 B10
A11 B11
GND GND
A12 B12
A13 B13
A14 B14
V
CC
V
CC
A15 B15
A16 B16
GND GND
A17 B17
OEBA CPBA
LEBA GND
001aaf040
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Table 2. Pin description
Symbol Pin Description
OEAB 1 A-to-B output enable input
LEAB 2 A-to-B latch enable input
A0 3 data input/output A0
GND 4 ground (0 V)
A1 5 data input/output A1
A2 6 data input/output A2
V
CC
7 supply voltage
74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 29 May 2006 5 of 19
Philips Semiconductors
74LVT16500A
3.3 V 18-bit universal bus transceiver; 3-state
A3 8 data input/output A3
A4 9 data input/output A4
A5 10 data input/output A5
GND 11 ground (0 V)
A6 12 data input/output A6
A7 13 data input/output A7
A8 14 data input/output A8
A9 15 data input/output A9
A10 16 data input/output A10
A11 17 data input/output A11
GND 18 ground (0 V)
A12 19 data input/output A12
A13 20 data input/output A13
A14 21 data input/output A14
V
CC
22 supply voltage
A15 23 data input/output A15
A16 24 data input/output A16
GND 25 ground (0 V)
A17 26 data input/output A17
OEBA 27 B-to-A output enable input (active LOW)
LEBA 28 B-to-A latch enable input
GND 29 ground (0 V)
CPBA 30 B-to-A clock input (active falling edge)
B17 31 data input/output B17
GND 32 ground (0 V)
B16 33 data input/output B16
B15 34 data input/output B15
V
CC
35 supply voltage
B14 36 data input/output B14
B13 37 data input/output B13
B12 38 data input/output B12
GND 39 ground (0 V)
B11 40 data input/output B11
B10 41 data input/output B10
B9 42 data input/output B9
B8 43 data input/output B8
B7 44 data input/output B7
B6 45 data input/output B6
GND 46 ground (0 V)
B5 47 data input/output B5
B4 48 data input/output B4
Table 2. Pin description
…continued
Symbol Pin Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

74LVT16500ADGG,112

Mfr. #:
Buy 74LVT16500ADGG,112
Manufacturer:
NXP Semiconductors
Description:
Bus Transceivers 3.3V 18-BIT UNIVRSAL
Lifecycle:
New from this manufacturer.
Delivery:
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