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ADCMP604BKSZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P14
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply LVDS Comparators
Data Sheet
ADCMP604/ADCMP605
FEATURES
Fully specified rail to rail at V
CCI
= 2.5 V to 5.5 V
Input common-mode voltage from −0.2 V to V
CCI
+ 0.2 V
Low glitch LVDS-compatible output stage
1.6 ns propagation delay
37 mW at 2.5 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection > 60 dB
−40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
FUNCTIONAL BLOCK DIAGRAM
V
P
NONINVERTING
INPUT
V
N
INVERTING
INPUT
S
DN
INPUT
Q OUTPUT
V
CCO
(ADCMP605 ONLY)
V
CCI
Q OUTPUT
LE/HYS INPUT
(ADCMP605
ONLY)
ADCMP604/
ADCMP605
LVDS
05916-001
Figure 1.
GENERAL DESCRIPTION
The ADCMP604/ADCMP605 are very fast comparators fabricated
on the Analog Devices, Inc. proprietary XFCB2 process. These
comparators are exceptionally versatile and easy to use. Features
include an input range from V
EE
− 0.5 V to V
CCI
+ 0.2 V, low noise,
LVDS-compatible output drivers, and TTL/CMOS latch inputs
with adjustable hysteresis and/or shut-down inputs.
The devices offer 1.5 ns propagation delays with 1 ps rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 50 ps.
A flexible power supply scheme allows the devices to operate
with a single 2.5 V positive supply and a −0.5 V to +2.7 V input
signal range up to a 5.5 V positive supply with a −0.5 V to +5.7 V
input signal range. Split input/output supplies, with no sequencing
restrictions on the ADCMP605, support a wide input signal
range with greatly reduced power consumption.
The LVDS-compatible output stage is designed to drive any
standard LVDS input. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded. High
speed latch and programmable hysteresis features are also provided
in a unique single-pin control option.
The ADCMP604 is available in a 6-lead SC70 package, and the
ADCMP605 is available in a 12-lead LFCSP.
Rev. C
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2015 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
ADCMP604/ADCMP605 Data Sheet
Rev. C | Page 2 of 14
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Timing Information ......................................................................... 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Applications Information .............................................................. 10
Power/Ground Layout and Bypassing ..................................... 10
LVDS-Compatible Output Stage .............................................. 10
Using/Disabling the Latch Feature ........................................... 10
Optimizing Performance ........................................................... 10
Comparator Propagation Delay Dispersion ........................... 11
Comparator Hysteresis .............................................................. 11
Crossover Bias Points ................................................................. 12
Minimum Input Slew Rate Requirement ................................ 12
Typical Application Circuits ......................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
1/15—Rev. B to Rev. C
Changes to Figure 4 .......................................................................... 7
Change to Figure 16 Caption .......................................................... 9
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
11/14—Rev. A to Rev. B
Changes to Figure 4 and Table 6 ..................................................... 7
Changes to Figure 15 and Figure 16 ............................................... 9
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
8/07—Rev. 0 to Rev. A
Changes to Features and General Description .............................. 1
Changes to Electrical Characteristics Section ............................... 3
Changes to Table 3 ............................................................................. 6
Changes to Layout ............................................................................. 7
Changes to Figure 8 ........................................................................... 8
Changes to Figure 14 ......................................................................... 9
Changes to Power/Ground Layout and Bypassing Section, and
Using/Disabling the Latch Feature Section ................................. 10
Changes to Comparator Hysteresis Section ................................ 11
Changes to Crossover Bias Points Section .................................. 12
Changes to Ordering Guide .......................................................... 14
10/06—Revision 0: Initial Version
Data Sheet ADCMP604/ADCMP605
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
CCI
= V
CCO
= 2.5 V, T
A
= −40°C to +125°C, typical at T
A
= 25 °C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
DC INPUT CHARACTERISTICS
Voltage Range V
P
, V
N
V
CCI
= 2.5 V to 5.5 V −0.5 V
CCI
+ 0.2 V
Common-Mode Range V
CCI
= 2.5 V to 5.5 V −0.2 V
CCI
+ 0.2 V
Differential Voltage V
CCI
= 2.5 V to 5.5 V V
CCI
V
Offset Voltage V
OS
−5.0 +5.0 mV
Bias Current I
P
, I
N
−5.0 ±2 +5.0 µA
Offset Current −2.0 +2.0 µA
Capacitance C
P
, C
N
1 pF
Resistance, Differential Mode −0.1 V to V
CCI
200 750 7500 kΩ
Resistance, Common Mode −0.5 V to V
CCI
+ 0.5 V 100 370 4000 kΩ
Active Gain A
V
62 dB
Common-Mode Rejection Ratio CMRR V
CCI
= 2.5 V, V
CCO
= 2.5 V,
V
CM
= −0.2 V to +2.7 V
50 dB
V
CCI
= 2.5 V, V
CCO
= 5.0 V
50
dB
Hysteresis
R
HYS
= ∞
<0.1
mV
LATCH ENABLE PIN CHARACTERISTICS
(ADCMP605 ONLY )
V
IH
Hysteresis is shut off
2.0
CCO
V
V
IL
Latch mode guaranteed −0.2 +0.4 +0.8 V
I
IH
V
IH
= V
CCO
+ 0.2 V −6 +6 µA
I
IL
V
IL
= 0.4 V −0.1 +0.1 mA
HYSTERESIS MODE AND TIMING (ADCMP605 ONLY )
Hysteresis Mode Bias Voltage Current sink −1 µA 1.145 1.25 1.40 V
Minimum Resistor Value Hysteresis = 120 mV 30 110 kΩ
Hysteresis Current Hysteresis = 120 mV −25 −8 µA
Latch Setup Time t
S
V
OD
= 50 mV −2 ns
Latch Hold Time t
H
V
OD
= 50 mV 2.7 ns
Latch-to-Output Delay t
PLOH
, t
PLOL
V
OD
= 50 mV 20 ns
Latch Minimum Pulse Width t
PL
V
OD
= 50 mV 24 ns
SHUTDOWN PIN CHARACTERISTICS (ADCMP605 ONLY )
V
IH
Comparator is operating 2.0 V
CCO
V
V
IL
Shutdown guaranteed −0.2 +0.4 +0.6 V
I
IH
V
IH
= V
CCO
−6 +6 µA
I
IL
V
IL
= 0 V
mA
Sleep Time t
SD
10% output swing 1.4 ns
Wake-Up Time t
H
V
OD
= 50 mV, output valid 25 ns
DC OUTPUT CHARACTERISTICS VCCI = VCCO = 2.5 V to 5.0 V
(ADCMP604)
V
CCO
= 2.5 V to 5.0 V (ADCMP605)
Differential Output Voltage Level V
OD
R
LOAD
= 100 Ω 245 350 445 mV
ΔV
OD
R
LOAD
= 100 Ω 50 mV
Common-Mode Voltage V
OCI
R
LOAD
= 100 Ω 1.125 1.375 V
Peak-to-Peak Common-Mode Output V
OC (p-p)
R
LOAD
= 100 Ω 50 mV
Rev. C | Page 3 of 14
P1-P3P4-P6P7-P9P10-P12P13-P14

ADCMP604BKSZ-REEL7

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Analog Devices Inc.
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Analog Comparators RR Fast 2.5-5.5V SGL-Supply LVDS
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