ADCMP604BKSZ-REEL7 Datasheet ADCMP604BKSZ-REEL7, ADCMP605BCPZ-R7, ADCMP604BKSZ-R2 | P10-P12

ADCMP604/ADCMP605 Data Sheet

APPLICATIONS INFORMATION

POWER/GROUND LAYOUT AND BYPASSING

The ADCMP604/ADCMP605 comparators are very high speed

devices. Despite the low noise output stage, it is essential to use

proper high speed design techniques to achieve the specified

performance. Because comparators are uncompensated amplifiers,

feedback in any phase relationship is likely to cause oscillations

or undesired hysteresis. The use of low impedance supply planes is

of critical importance particularly the output supply plane (V

CCO

)

and the ground plane (GND). Individual supply planes are

recommended as part of a multilayer board. Providing the

lowest inductance return path for switching currents ensures

the best possible performance in the target application.

It is also important to adequately bypass the input and output

supplies. Multiple high quality 0.01 µF bypass capacitors should

be placed as close as possible to each of the V

CCI

and V

CCO

supply

pins and should be connected to the GND plane with redundant

vias. At least one of these should be placed to provide a physically

short return path for output currents flowing back from ground

to the V

CCI

pin and the V

CCO

pin. High frequency bypass capacitors

should be carefully selected for minimum inductance and ESR.

Parasitic layout inductance should also be strictly controlled to

maximize the effectiveness of the bypass at high frequencies.

If the package allows, and the input and output supplies have

been connected separately (V

CCI

≠ V

CCO

), be sure to bypass each

of these supplies separately to the GND plane. Do not connect a

bypass capacitor between these supplies. It is recommended that

the GND plane separate the V

CCI

and V

CCO

planes when the

circuit board layout is designed to minimize coupling between

the two supplies to take advantage of the additional bypass

capacitance from each respective supply to the ground plane.

This enhances the performance when split input/output supplies

are used. If the input and output supplies are connected together

for single-supply operation (V

CCI

= V

CCO

), coupling between the

two supplies is unavoidable; however, careful board placement

can help keep output return currents away from the inputs.

LVDS-COMPATIBLE OUTPUT STAGE

Specified propagation delay dispersion performance is only

achieved by keeping parasitic capacitive loads at or below the

specified minimums. The outputs of the ADCMP604 and

ADCMP605 are designed to directly drive any standard

LVDS-compatible input.

USING/DISABLING THE LATCH FEATURE

The latch input is designed for maximum versatility. It can safely be

left floating or it can be driven low by any standard TTL/CMOS

device as a high speed latch. In addition, the pin can be operated as

a hysteresis control pin with a bias voltage of 1.25 V nominal and

an input resistance of approximately 70 kΩ. This allows the

comparator hysteresis to be easily controlled by either a resistor or

an inexpensive CMOS DAC. Driving this pin high or floating the

pin disables all hysteresis.

Hysteresis control and latch mode can be used together if an

open drain, an open collector, or a three-state driver is connected in

parallel to the hysteresis control resistor or current source.

Due to the programmable hysteresis feature, the logic threshold

of the latch pin is approximately 1.1 V, regardless of V

CCO

OPTIMIZING PERFORMANCE

As with any high speed comparator, proper design and layout

techniques are essential for obtaining the specified performance.

Stray capacitance, inductance, inductive power and ground

impedances, or other layout issues can severely limit performance

and often cause oscillation. Large discontinuities along input

and output transmission lines can also limit the specified

pulse-width dispersion performance. The source impedance

should be minimized as much as is practicable. High source

impedance, in combination with the parasitic input capacitance

of the comparator, causes an undesirable degradation in bandwidth

at the input, thus degrading the overall response. Thermal noise

from large resistances can easily cause extra jitter with slowly

slewing input signals. Higher impedances encourage undesired

coupling.

Rev. C | Page 10 of 14

Data Sheet ADCMP604/ADCMP605

Rev. C | Page 11 of 14

COMPARATOR PROPAGATION DELAY

DISPERSION

The ADCMP604/ADCMP605 comparators are designed to reduce

propagation delay dispersion over a wide input overdrive range

of 5 mV to V

CCI

− 1 V. Propagation delay dispersion is the variation

in propagation delay that results from a change in the degree of

overdrive or slew rate (how far or how fast the input signal is

driven past the switching threshold).

Propagation delay dispersion is a specification that becomes

important in high speed, time-critical applications, such as data

communications, automatic test and measurement, and

instrumentation. It is also important in event-driven applications,

such as pulse spectroscopy, nuclear instrumentation, and

medical imaging. Dispersion is defined as the variation in

propagation delay as the input overdrive conditions are changed

(see Figure 17 and Figure 18).

The ADCMP604/ADCMP605 dispersion is typically <1.6 ns as

the overdrive varies from 10 mV to 125 mV. This specification

applies to both positive and negative signals because each of the

ADCMP604 and ADCMP605 has substantially equal delays for

positive-going and negative-going inputs and very low output

skews.

Q/Q OUTPUT

INPUT VOLTAGE

500mV OVERDRIVE

10mV OVERDRIVE

DISPERSION

± V

05916-016

Figure 17. Propagation Delay—Overdrive Dispersion

Q/Q OUTPUT

INPUT VOLTAGE

10V/ns

1V/ns

DISPERSION

± V

05916-017

Figure 18. Propagation Delay—Slew Rate Dispersion

COMPARATOR HYSTERESIS

The addition of hysteresis to a comparator is often desirable in a

noisy environment, or when the differential input amplitudes

are relatively small or slow moving. The transfer function for a

comparator with hysteresis is shown in Figure 19. As the input

voltage approaches the threshold (0 V, in this example) from

below the threshold region in a positive direction, the comparator

switches from low to high when the input crosses +V

/2. The

new switching threshold becomes −V

/2. The comparator remains

in the high state until the threshold, −V

/2, is crossed from

below the threshold region in a negative direction. In this manner,

noise or feedback output signals centered on 0 V input cannot

cause the comparator to switch states unless it exceeds the region

bounded by ±V

/2.

OUTPUT

INPUT

–V

05916-018

Figure 19. Comparator Hysteresis Transfer Function

The customary technique for introducing hysteresis into a

comparator uses positive feedback from the output back to the

input. One limitation of this approach is that the amount of

hysteresis varies with the output logic levels, resulting in

hysteresis that is not symmetric about the threshold. The

external feedback network can also introduce significant

parasitics that reduce high speed performance and induce

oscillation in some cases.

The ADCMP605 comparator offers a programmable hysteresis

feature that significantly improves accuracy and stability.

Connecting an external pull-down resistor or a current source

from the LE/HYS pin to GND varies the amount of hysteresis in

a predictable and stable manner. Leaving the LE/HYS pin

disconnected or driving it high removes hysteresis. The

maximum hysteresis that can be applied using this pin is

approximately 160 mV. Figure 20 illustrates the amount of

hysteresis applied as a function of external resistor value. Figure 11

illustrates hysteresis as a function of current.

ADCMP604/ADCMP605 Data Sheet

The hysteresis control pin appears as a 1.25 V bias voltage seen

through a series resistance of 70 kΩ ± 20% throughout the

hysteresis control range. The advantages of applying hysteresis

in this manner are improved accuracy, improved stability, reduced

component count, and maximum versatility. An external bypass

capacitor is not recommended on the HYS pin because it would

likely degrade the jitter performance of the device and impair the

latch function. As described in the Using/Disabling the Latch

Feature section, hysteresis control need not compromise the

latch function.

100

150

200

250

50 100 150 200 250 300 350 400 450 500

HYSTERESIS RESISTOR (kΩ)

HYSTERESIS (mV)

= 2.5V

= 5.5V

05916-026

Figure 20. Hysteresis vs. R

HYS

Control Resistor

CROSSOVER BIAS POINTS

Rail-to-rail inputs of this type, in both op amps and comparators,

have a dual front-end design. Certain devices are active near the

CCI

rail and others are active near the V

rail. At some

predetermined point in the common-mode range, a crossover

occurs. At this point, normally V

CCI

/2, the direction of the bias

current reverses and there are changes in measured offset

voltages and currents.

MINIMUM INPUT SLEW RATE REQUIREMENT

With the rated load capacitance and normal good PCB design

practice, as discussed in the Optimizing Performance section,

these comparators should be stable at any input slew rate with

no hysteresis. Broadband noise from the input stage is observed

in place of the violent chattering seen with most other high

speed comparators. With additional capacitive loading or poor

bypassing, oscillation is observed. This oscillation is due to the

high gain bandwidth of the comparator in combination with

feedback parasitics in the package and PCB. In many applications,

chattering is not harmful.

Rev. C | Page 12 of 14

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

ADCMP604BKSZ-REEL7

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Analog Comparators RR Fast 2.5-5.5V SGL-Supply LVDS

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