ADCMP604/ADCMP605 Data Sheet
Rev. C | Page 14 of 14
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-203-AB
0.22
0.08
0.30
0.15
1.00
0.90
0.70
SEATING
PLANE
4 5 6
3 2 1
PIN 1
0.65 BSC
1.30 BSC
0.10 MAX
0.10 COPLANARITY
0.40
0.10
1.10
0.80
2.20
2.00
1.80
2.40
2.10
1.80
1.35
1.25
1.15
0.46
0.36
0.26
Figure 27. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
1.45
1.30 SQ
1.15
111808-A
1
0.50
BSC
BOTTOM VIEWTOP VIEW
12
4
6
7
9
10
3
EXPOSED
PAD
P
I
N
1
I
N
D
I
C
A
T
O
R
3.10
3.00 SQ
2.90
0.70
0.60
0.50
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.30
0.23
0.18
COMPLIANT
TO
JEDEC STANDARDS MO-220-WEED.
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.80
0.75
0.70
Figure 28. 12-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-12-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description
Package
Option Branding
ADCMP604BKSZ-R2 −40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 G0Q
ADCMP604BKSZ-REEL7 −40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 G0Q
ADCMP604BKSZ-RL −40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 G0Q
EVAL-ADCMP604BKSZ Evaluation Board
ADCMP605BCPZ-WP −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-12-4 G0K
ADCMP605BCPZ-R2 −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-12-4 G0K
ADCMP605BCPZ-R7 −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-12-4 G0K
EVAL-ADCMP605BCPZ Evaluation Board
1
Z = RoHS Compliant Part
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D05916-0-1/15(C)
