REV. D
AD7713
–5–
TIMING CHARACTERISTICS
1, 2
(DV
DD
= 5 V ⴞ 5%; AV
DD
= 5 V or 10 V ⴞ 5%; AGND = DGND = 0 V; f
CLKIN
= 2 MHz;
Input Logic 0 = 0 V, Logic 1 = DV
DD
, unless otherwise noted.)
Limit at T
MIN
, T
MAX
Parameter (A, S Versions) Unit Conditions/Comments
f
CLK IN
3, 4
400 kHz min Master Clock Frequency: Crystal Oscillator or
2 MHz max Externally Supplied for Specified Performance
t
CLK IN LO
0.4 ⫻ t
CLK IN
ns min Master Clock Input Low Time; t
CLK IN
= 1/f
CLK IN
t
CLK IN HI
0.4 ⫻ t
CLK IN
ns min Master Clock Input High Time
t
r
5
50 ns max Digital Output Rise Time; Typically 20 ns
t
f
5
50 ns max Digital Output Fall Time; Typically 20 ns
t
1
1000 ns min SYNC Pulse Width
Self-Clocking Mode
t
2
0 ns min DRDY to RFS Setup Time
t
3
0 ns min DRDY to RFS Hold Time
t
4
2 ⫻ t
CLK IN
ns min A0 to RFS Setup Time
t
5
0 ns min A0 to RFS Hold Time
t
6
4 ⫻ t
CLK IN
+ 20 ns max RFS Low to SCLK Falling Edge
t
7
6
4 ⫻ t
CLK IN
+20 ns max Data Access Time (RFS Low to Data Valid)
t
8
6
t
CLK IN
/2 ns min SCLK Falling Edge to Data Valid Delay
t
CLK IN
/2 + 30 ns max
t
9
t
CLK IN
/2 ns nom SCLK High Pulse Width
t
10
3 ⫻ t
CLK IN
/2 ns nom SCLK Low Pulse Width
t
14
50 ns min A0 to TFS Setup Time
t
15
0 ns min A0 to TFS Hold Time
t
16
4 ⫻ t
CLK IN
+ 20 ns max TFS to SCLK Falling Edge Delay Time
t
17
4 ⫻ t
CLK IN
ns min TFS to SCLK Falling Edge Hold Time
t
18
0 ns min Data Valid to SCLK Setup Time
t
19
10 ns min Data Valid to SCLK Hold Time
External-Clocking Mode
f
SCLK
f
CLK IN
/5 MHz max Serial Clock Input Frequency
t
20
0 ns min DRDY to RFS Setup Time
t
21
0 ns min DRDY to RFS Hold Time
t
22
2 ⫻ t
CLK IN
ns min A0 to RFS Setup Time
t
23
0 ns min A0 to RFS Hold Time
t
24
6
4 ⫻ t
CLK IN
ns max Data Access Time (RFS Low to Data Valid)
t
25
6
10 ns min SCLK Falling Edge to Data Valid Delay
2 ⫻ t
CLK IN
+ 20 ns max
t
26
2 ⫻ t
CLK IN
ns min SCLK High Pulse Width
t
27
2 ⫻ t
CLK IN
ns min SCLK Low Pulse Width
t
28
t
CLK IN
+ 10 ns max SCLK Falling Edge to DRDY High
t
29
7
10 ns min SCLK to Data Valid Hold Time
t
CLK IN
+ 10 ns max
t
30
10 ns min RFS/TFS to SCLK Falling Edge Hold Time
t
31
7
5 ⫻ t
CLK IN
/2 + 50 ns max RFS to Data Valid Hold Time
t
32
0 ns min A0 to TFS Setup Time
t
33
0 ns min A0 to TFS Hold Time
t
34
4 ⫻ t
CLK IN
ns min SCLK Falling Edge to TFS Hold Time
t
35
2 ⫻ t
CLK IN
– SCLK High ns min Data Valid to SCLK Setup Time
t
36
30 ns min Data Valid to SCLK Hold Time
NOTES
1
Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 10 to 13.
3
CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7713 is not in standby mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.
4
The AD7713 is production tested with f
CLK IN
at 2 MHz. It is guaranteed by characterization to operate at 400 kHz.
5
Specified using 10% and 90% points on waveform of interest.
6
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
7
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
