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9ZML1233EKILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
1©2017 Integrated Device Technology, Inc. December 1, 2017
Description
The 9ZML1233E / 9ZML1253E are second generation enhanced
performance DB1200ZL derivatives. The parts are pin-compatible
upgrades to the 9ZML1232B, while offering much improved phase
jitter performance. A fixed external feedback maintains low drift for
critical QPI/UPI applications, while each input channel has software
adjustable input-to-output delay to ease transport delay
management for today's more complex server topologies. The
9ZML1233E and 9ZML1253E have an SMBus Write Lockout pin for
increased device and system security.
PCIe Clocking Architectures
Supported
▪ Common Clocked (CC)
▪ Independent Reference (IR) with and without spread spectrum
Typical Applications
▪ Servers
▪ Storage
▪ Networking
▪ SSDs
Output Features
▪ 12 Low-Power (LP) HCSL output pairs (1233E)
▪ 12 Low-Power (LP) HCSL output pairs with 85Ω Zout (1253E)
Features
▪ SMBus write lock feature; increases system security
▪ 2 software-configurable input-to-output delay lines; manage
transport delay for complex topologies
▪ LP-HCSL outputs; eliminate 24 resistors, save 41mm
2
of area
(1233E)
▪ LP-HCSL outputs with 85Ω Zout; eliminate 48 resistors, save
82mm
2
of area (1253E)
▪ 12 OE# pins; hardware control of each output
▪ 3 selectable SMBus addresses; multiple devices can share same
SMBus segment
▪ Selectable PLL bandwidths; minimizes jitter peaking in cascaded
PLL topologies
▪ Hardware/SMBus control of PLL bandwidth and bypass; change
mode without power cycle
▪ Spread spectrum compatible; tracks spreading input clock for EMI
reduction
▪ 100MHz PLL Mode; UPI support
▪ 10 x 10 mm 72-VFQFPN package; small board footprint
Key Specifications
▪ Cycle-to-cycle jitter < 50ps
▪ Output-to-output skew < 50ps
▪ Input-to-output delay: 0ps default
▪ Input-to-output delay variation < 50ps
▪ Phase jitter: PCIe Gen4 < 0.5ps rms
▪ Phase jitter: UPI > 9.6GB/s < 0.1ps rms
▪ Phase jitter: IF-UPI < 1.0ps rms
Block Diagram
Bypass path
Low Phase Noise
Z-PLL
(SS-Compatible)
I2O
Delay
12
outputs
CONTROL
NOTE: Internal series resistors are only
present on the 9ZML1253
^SEL_A_B#
DIF_INA
DIF_INB
^vHIBW_BYPM_LOBW#
CKPWRGD_PD#
vSMB_A0_tri
vSMB_WRTLOCK
SMBDAT
SMBCLK
^OE(11:0)#
DIF_0
FBOUT_NC
FBOUT_NC
DIF_0
DIF_INB
DIF_INA
DIF_11
DIF_11
2:12 DB1200ZL Derivative for
PCIe Gen1-4 and UPI
9ZML1233E / 9ZML1253E
Datasheet
2©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Pin Assignments
Pin Descriptions
^OE11#
^OE10#
GND
NC
DIF_11#
DIF_11
DIF_10#
DIF_10
VDD
GND
DIF_9#
DIF_9
DIF_8#
DIF_8
GND
NC
^OE9#
^OE8#
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
VDDA 1 54
^OE7#
GNDA 2 53
^OE6#
^SEL_A_B# 3 52
VDDIO
^vHIBW_BYPM_LOBW# 4 51
GND
CKPWRGD_PD# 5 50
DIF_7#
DIF_INB 6 49
DIF_7
DIF_INB# 7 48
DIF_6#
GND 8 47
DIF_6
VDDR 9 46
GND
DIF_INA 10 45
VDD
DIF_INA# 11 44
DIF_5#
vSADR0_tri 12 43
DIF_5
SMBDAT 13 42
DIF_4#
SMBCLK 14 41
DIF_4
vSMB_WRTLOCK 15 40
VDDIO
NC 16 39
GND
FBOUT_NC# 17 38
^OE5#
FBOUT_NC 18 37
^OE4#
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
^OE0#
^OE1#
NC
GND
DIF_0
DIF_0#
DIF_1
DIF_1#
GND
VDD
DIF_2
DIF_2#
DIF_3
DIF_3#
NC
GND
^OE2#
^OE3#
9ZML1233
9ZML1253
Connect EPAD to GND
^ prefix indicates internal 120kohm pull-up
v prefix indicates internal 120kohm pull-down
10 x 10 mm 72-VFQFPN 0.5mm pin pitch
Table 1. Pin Descriptions
Number Name Type Description
1V
DDA
Power Power supply for PLL core.
2 GNDA GND Ground pin for the PLL core.
3 ^SEL_A_B# Input
Input to select differential input clock A or differential input clock B. This input has an
internal 120kΩ pull-up resistor.
0 = input B selected, 1 = input A selected.
4 ^vHIBW_BYPM_LOBW#
Latched
In
Tri-level input to select High BW, Bypass or Low BW mode. This pin is biased to VDD/2
(Bypass Mode) with internal pull-up/pull-down resistors. See PLL Operating Mode
table for details.
5 CKPWRGD_PD# Input
3.3V input notifies device to sample latched inputs and start up on first high assertion,
or exit Power Down Mode on subsequent assertions. Low enters Power Down Mode.
6 DIF_INB Input True input of differential clock.
7 DIF_INB# Input Complement input of differential clock.
8 GND GND Ground pin.
9V
DDR
Power
Power supply for differential input clock (receiver). This V
DD
should be treated as an
analog power rail and filtered appropriately. Nominally 3.3V.
10 DIF_INA Input True input of differential clock.
3©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
11 DIF_INA# Input Complement input of differential clock.
12 vSADR0_tri Input
SMBus address bit. This is a tri-level input that works in conjunction with other SADR
pins, if present, to decode SMBus Addresses. It has an internal 120kΩ pull-down
resistor. See the SMBus Addressing table.
13 SMBDAT I/O Data pin of SMBUS circuitry.
14 SMBCLK Input Clock pin of SMBUS circuitry.
15 vSMB_WRTLOCK Input
This pin prevents SMBus writes when asserted. SMBus reads are not affected. This
pin has an internal 120kΩ pull-down.
0 = SMBus writes allows, 1 = SMBus writes blocked.
16 NC — No connection.
17 FBOUT_NC# Output
Complementary half of differential feedback output. This pin should NOT be connected
to anything outside the chip. It exists to provide delay path matching to get 0
propagation delay.
18 FBOUT_NC Output
True half of differential feedback output. This pin should NOT be connected to anything
outside the chip. It exists to provide delay path matching to get 0 propagation delay.
19 ^OE0# Input
Active low input for enabling output 0. This pin has an internal 120kΩ pull-up resistor.
1 = disable outputs, 0 = enable outputs.
20 ^OE1# Input
Active low input for enabling output 1. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
21 NC — No connection.
22 GND GND Ground pin.
23 DIF_0 Output HCSL true clock output.
24 DIF_0# Output HCSL complementary clock output.
25 DIF_1 Output HCSL true clock output.
26 DIF_1# Output HCSL complementary clock output.
27 GND GND Ground pin.
28 VDD Power Power supply, nominally 3.3V.
29 DIF_2 Output HCSL true clock output.
30 DIF_2# Output HCSL complementary clock output.
31 DIF_3 Output HCSL true clock output.
32 DIF_3# Output HCSL complementary clock output.
33 NC — No connection.
34 GND GND Ground pin.
35 ^OE2# Input
Active low input for enabling output 2. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
36 ^OE3# Input
Active low input for enabling output 3. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
Table 1. Pin Descriptions (Cont.)
Number Name Type Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

9ZML1233EKILF

Mfr. #:
Buy 9ZML1233EKILF
Manufacturer:
IDT
Description:
Clock Buffer DB1200ZL OEM MUX DERIV +WRTLK
Lifecycle:
New from this manufacturer.
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