10©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Table 9. Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures
Parameter Symbol Conditions Minimum Typical Maximum
Industry
Limits
Units Notes
Phase Jitter,
PLL Mode
t
jphPCIeG1-CC
PCIe Gen 1. 13 30 86
ps
(p-p)
1, 2,
3, 6
t
jphPCIeG2-CC
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz
(PLL BW of 5–16MHz or 8–16MHz,
CDR = 5MHz).
0.25 0.7 3
ps
(rms)
1, 2, 6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5–16MHz or 8–16MHz,
CDR = 5MHz).
1.00 1.5 3.1
ps
(rms)
1, 2, 6
t
jphPCIeG3-CC
PCIe Gen 3
(PLL BW of 2–4MHz or 2–5MHz,
CDR = 10MHz).
0.24 0.35 1
ps
(rms)
1, 2, 6
t
jphPCIeG4-CC
PCIe Gen 4
(PLL BW of 2–4MHz or 2–5MHz,
CDR = 10MHz).
0.24 0.35 0.5
ps
(rms)
1, 2, 6
Additive
Phase Jitter,
Bypass Mode
t
jphPCIeG1-CC
PCIe Gen 1. 0.0 0.05
Not
Applicable
ps
(p-p)
1, 2,
3, 4, 6
t
jphPCIeG2-CC
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz
(PLL BW of 5–16MHz or 8–16MHz,
CDR = 5MHz).
0.00 0.05
ps
(rms)
1, 2,
3, 4, 6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5–16MHz or 8–16MHz,
CDR = 5MHz).
0.00 0.05
ps
(rms)
1, 2,
3, 4, 6
t
jphPCIeG3-CC
PCIe Gen 3
(PLL BW of 2–4MHz or 2–5MHz,
CDR = 10MHz).
0.00 0.05
ps
(rms)
1, 2,
3, 4, 6
t
jphPCIeG4-CC
PCIe Gen 4
(PLL BW of 2–4MHz or 2–5MHz,
CDR = 10MHz).
0.00 0.05
ps
(rms)
1, 2,
3, 4, 6
11©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Notes for PCIe Filtered Phase Jitter tables:
1
Applies to all differential outputs when driven by 9SQL495x or equivalent, guaranteed by design and characterization.
2
Calculated from Intel-supplied clock jitter tool, when driven by 9SQL495x or equivalent with spread on and off.
3
Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1
–12
.
4
For RMS values, additive jitter is calculated by solving the following equation for b [b = sqrt(c
2
- a
2
)] where “a” is rms input jitter and
“c” is rms total jitter.
5
IR is the new name for Separate Reference Independent Spread (SRIS) and Separate Reference no Spread (SRNS) PCIe clock
architectures. According to the PCIe Base Specification Rev4.0 version 0.7 draft, the jitter transfer functions and corresponding jitter
limits are not defined for the IR clock architecture. Widely accepted industry limits using widely accepted industry filters are used to
populate this table. There are no accepted filters or limits for IR clock architectures at PCIe Gen1 or Gen4 data rates.
Table 10. Filtered Phase Jitter Parameters - PCIe Independent Reference (IR) Architectures
Parameter Symbol Conditions Minimum Typical Maximum
Industry
Limits
Units Notes
Phase Jitter,
PLL Mode
t
jphPCIeG2-SRIS
PCIe Gen 2
(PLL BW of 16MHz, CDR = 5MHz).
0.8 1.2 2
ps
(rms)
1, 2, 5
t
jphPCIeG3-SRIS
PCIe Gen 3
(PLL BW of 2–4MHz, CDR =
10MHz).
0.64 0.68 0.7
ps
(rms)
1, 2, 5
Additive
Phase Jitter,
Bypass Mode
t
jphPCIeG2-SRIS
PCIe Gen 2
(PLL BW of 16MHz, CDR = 5MHz).
0.00 0.02
Not
Applicable
ps
(rms)
2, 4, 5
t
jphPCIeG3-SRIS
PCIe Gen 3
(PLL BW of 2–4MHz, CDR =
10MHz).
0.00 0.02
ps
(rms)
2, 4, 5
Table 11. Filtered Phase Jitter Parameters – QPI/UPI
Parameter Symbol Conditions Minimum Typical Maximum
Industry
Limits
Units Notes
Phase Jitter,
PLL Mode
t
jphQPI_UPI
QPI & UPI
(100MHz or 133MHz, 4.8Gb/s,
6.4Gb/s 12UI).
0.15 0.3 0.5
ps
(rms)
1, 2
QPI & UPI
(100MHz, 8.0Gb/s, 12UI).
0.08 0.1 0.3
ps
(rms)
1, 2
QPI & UPI
(100MHz, >
9.6Gb/s, 12UI).
0.07 0.1 0.2
ps
(rms)
1, 2
t
jphIF-UPI
IF-UPI.
0.1
0.17
0.15
0.2
1
ps
(rms)
1, 4,
5
12©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
1
Applies to all differential outputs, guaranteed by design and characterization.
2
Calculated from Intel-supplied clock jitter tool, when driven by 9SQL495x or equivalent with spread on and off.
3
Additive jitter for RMS values is calculated by solving for b [b = sqrt(c
2
- a
2
)] where “a” is rms input jitter and “c” is rms total jitter.
4
Calculated from phase noise analyzer when driven by Wenzel Associates source with Intel-specified brick-wall filter applied.
5
Top number is when the buffer is in Low BW mode, bottom number is when the buffer is in High BW mode.
1
Applies to all outputs when driven by Wenzel clock source.
2
12kHz to 20MHz brick wall filter.
3
For RMS values, additive jitter is calculated by solving for b [a^2 + b^2 = c^2] where “a” is rms input jitter and “c” is rms total jitter.
Power Management
Additive
Phase Jitter,
Bypass Mode
t
jphQPI_UPI
QPI & UPI
(100MHz or 133MHz, 4.8Gb/s,
6.4Gb/s 12UI).
0.00 0.03
Not
Applicable
ps
(rms)
1, 2,
3
QPI & UPI
(100MHz, 8.0Gb/s, 12UI).
0.02 0.07
ps
(rms)
1, 2,
3
QPI & UPI
(100MHz, >
9.6Gb/s, 12UI).
0.02 0.06
ps
(rms)
1, 2,
3
t
jphIF-UPI
IF-UPI. 0.06 0.08
ps
(rms)
1, 4
Table 12. Unfiltered Phase Jitter Parameters – 12kHz to 20MHz
Parameter Symbol Conditions Minimum Typical Maximum
Industry
Limits
Units Notes
Phase Jitter, PLL
Mode
t
jph12k-20MHi
PLL High BW, SSC Off,
100MHz.
171 250
Not
applicable
fs
(rms)
1,2
Phase Jitter, PLL
Mode
t
jph12k-20MLo
PLL Low BW, SSC Off,
100MHz.
183 250
fs
(rms)
1,2
Additive Phase
Jitter, Bypass Mode
t
jph12k-20MByp
Bypass Mode, SSC Off,
100MHz.
109 150
fs
(rms)
1,2,3
Inputs Control Bits Outputs
PLL State
CKPWRGD_PD# DIF_IN SMBus EN bit DIF_x FBOUT_NC
0 X X Low/Low Low/Low Off
1 Running
0 Low/Low Running On
1 Running Running On
Table 11. Filtered Phase Jitter Parameters – QPI/UPI (Cont.)
Parameter Symbol Conditions Minimum Typical Maximum
Industry
Limits
Units Notes

9ZML1233EKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer DB1200ZL OEM MUX DERIV +WRTLK
Lifecycle:
New from this manufacturer.
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