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9ZML1233EKILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
4©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
37 ^OE4# Input
Active low input for enabling output 4. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
38 ^OE5# Input
Active low input for enabling output 5. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
39 GND GND Ground pin.
40 V
DDIO
Power Power supply for differential outputs.
41 DIF_4 Output HCSL true clock output.
42 DIF_4# Output HCSL complementary clock output.
43 DIF_5 Output HCSL true clock output.
44 DIF_5# Output HCSL complementary clock output.
45 V
DD
PWR Power supply, nominally 3.3V.
46 GND GND Ground pin.
47 DIF_6 Output HCSL true clock output.
48 DIF_6# Output HCSL complementary clock output.
49 DIF_7 Output HCSL true clock output.
50 DIF_7# Output HCSL complementary clock output.
51 GND GND Ground pin.
52 V
DDIO
Power Power supply for differential outputs.
53 ^OE6# Input
Active low input for enabling output 6. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
54 ^OE7# Input
Active low input for enabling output 7. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
55 ^OE8# Input
Active low input for enabling output 8. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
56 ^OE9# Input
Active low input for enabling output 9. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
57 NC — No connection.
58 GND GND Ground pin.
59 DIF_8 Output HCSL true clock output.
60 DIF_8# Output HCSL complementary clock output.
61 DIF_9 Output HCSL true clock output.
62 DIF_9# Output HCSL complementary clock output.
63 GND GND Ground pin.
64 V
DD
Power Power supply, nominally 3.3V.
65 DIF_10 Output HCSL true clock output.
Table 1. Pin Descriptions (Cont.)
Number Name Type Description
5©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9ZML1233E / 9ZML1253E. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 4.6V.
66 DIF_10# Output HCSL complementary clock output.
67 DIF_11 Output HCSL true clock output.
68 DIF_11# Output HCSL complementary clock output.
69 NC — No connection.
70 GND GND Ground pin.
71 ^OE10# Input
Active low input for enabling output 10. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
72 ^OE11# Input
Active low input for enabling output 11. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
73 EPAD GND Connect to ground.
Table 2. Absolute Maximum Ratings
Parameter Symbol Conditions Minimum Typical Maximum Units Notes
Supply Voltage V
DDx
4.6 V 1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
Except for SMBus interface. V
DD
+ 0.5 V 1,3
Input High Voltage V
IHSMB
SMBus clock and data pins. 5.5 V 1
Storage Temperature Ts -65 150
°
C1
Junction Temperature Tj 125 °C 1
Input ESD Protection ESD prot Human Body Model. 2000 V 1
Table 1. Pin Descriptions (Cont.)
Number Name Type Description
6©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Electrical Characteristics
Over specified temperature and voltage ranges unless otherwise indicated; see Test Loads for loading conditions.
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are > 200mV.
4
DIF_IN input.
5
The differential input clock must be running for the SMBus to be active.
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through ±75mV window centered around differential zero.
Table 3. SMBus Parameters
Parameter Symbol Conditions Minimum Typical Maximum Units Notes
SMBus Input Low Voltage V
ILSMB
0.8 V
SMBus Input High Voltage V
IHSMB
2.1 V
DDSMB
V
SMBus Output Low Voltage V
OLSMB
At I
PULLUP.
0.4 V
SMBus Sink Current I
PULLUP
At V
OL.
4mA
Nominal Bus Voltage V
DDSMB
2.7 3.6 V 1
SCLK/SDATA Rise Time t
RSMB
(Max V
IL
- 0.15V) to (Min V
IH
+ 0.15V). 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min V
IH
+ 0.15V) to (Max V
IL
- 0.15V). 300 ns 1
SMBus Operating Frequency f
MAXMB
Maximum SMBus operating frequency. 400 kHz 5
Table 4. DIF_IN Clock Input Parameters
Parameter Symbol Conditions Minimum Typical Maximum Units Notes
Input Crossover Voltage V
CROSS
Cross over voltage. 150 900 mV 1
Input Swing – DIF_IN V
SWING
Differential value. 300 mV 1
Input Slew Rate – DIF_IN dv/dt Measured differentially. 0.35 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND. -5 5 μA
Input Duty Cycle d
tin
Measurement from differential
waveform.
45 55 % 1
Input Jitter –Cycle to Cycle J
DIFIn
Differential measurement. 0 125 ps 1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

9ZML1233EKILF

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Buy 9ZML1233EKILF
Manufacturer:
IDT
Description:
Clock Buffer DB1200ZL OEM MUX DERIV +WRTLK
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