16©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
General SMBus Serial Interface Information
How to Write
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a stop bit
9ZML1233E / 9ZML1253E SMBus Addressing
How to Read
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X
(H)
was written to
Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
OO
OO
O
Byte N + X - 1
ACK
PstoP bit
SMB_A0_tri SMBus Address (Read/Write bit = 0)
0D8
MDA
1DE
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
T starT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
OO
OO
O
Byte N + X - 1
N Not acknowledge
PstoP bit
17©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
SMBus Table: PLL Mode and Frequency Select Register
Note: Changing the PLL operating mode between HiBW or LoBW and Bypass mode or between Bypass mode and HiBW or LoBW
requires a system reset. Changing the PLL operating mode between HiBW and LoBw or between LoBW and HiBW does not require a
system reset.
SMBus Table: Output Disable Register
SMBus Table: Output Control Register
Byte 0 Name Control Function Type 0 1 Default
Bit 7 PLL Mode bit [1] PLL Operating Mode Rd back 1 R
See PLL Operating Mode table
Latch
Bit 6 PLL Mode bit [0] PLL Operating Mode Rd back 0 R Latch
Bit 5 SEL_A_B# Input Select Readback R DIF_INB DIF_INA Real
Bit 4 Reserved 0
Bit 3 PLL_InSEL_SW_EN
Enable S/W control of PLL BW and
Input select
RW Pin Control SMBus Control 0
Bit 2 PLL Mode bit [1] PLL Operating Mode 1 RW
See PLL Operating Mode table
1
1
Bit 1 PLL Mode bit [0] PLL Operating Mode 1 RW 1
Bit 0 Reserved 1
Byte 1 Name Control Function Type 0 1 Default
Bit 7 DIF_7_En Output Control overrides OE# pin RW
Low/Low Pin Control
1
Bit 6 DIF_6_En Output Control overrides OE# pin RW 1
Bit 5 DIF_5_En Output Control overrides OE# pin RW 1
Bit 4 DIF_4_En Output Control overrides OE# pin RW 1
Bit 3 DIF_3_En Output Control overrides OE# pin RW 1
Bit 2 DIF_2_En Output Control overrides OE# pin RW 1
Bit 1 DIF_1_En Output Control overrides OE# pin RW 1
Bit 0 DIF_0_En Output Control overrides OE# pin RW 1
Byte 2 Name Control Function Type 0 1 Default
Bit 7
Reserved 0
Bit 6 Reserved 0
Bit 5
Reserved 0
Bit 4 Reserved 0
Bit 3 DIF_11_En Output Control overrides OE# pin RW
Low/Low Pin Control
1
Bit 2 DIF_10_En Output Control overrides OE# pin RW 1
Bit 1 DIF_9_En Output Control overrides OE# pin RW 1
Bit 0 DIF_8_En Output Control overrides OE# pin RW 1
18©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
SMBus Table: Reserved Register
SMBus Table: Reserved Register
SMBus Table: Vendor & Revision ID Register
Byte 3 Name Control Function Type 0 1 Default
Bit 7
Reserved 0
Bit 6
Reserved 0
Bit 5 Reserved 0
Bit 4
Reserved 0
Bit 3 Reserved 0
Bit 2 Reserved 0
Bit 1
Reserved 0
Bit 0 Reserved 0
Byte 4 Name Control Function Type 0 1 Default
Bit 7
Reserved 0
Bit 6 Reserved 0
Bit 5 Reserved 0
Bit 4
Reserved 0
Bit 3 Reserved 0
Bit 2
Reserved 0
Bit 1 Reserved 0
Bit 0 Reserved 0
Byte 5 Name Control Function Type 0 1 Default
Bit 7 RID3
REVISION ID
R
E rev = 0100
0
Bit 6 RID2 R 1
Bit 5 RID1 R 0
Bit 4 RID0 R 0
Bit 3 VID3
VENDOR ID
R— 0
Bit 2 VID2 R 0
Bit 1 VID1 R 0
Bit 0 VID0 R 1

9ZML1233EKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer DB1200ZL OEM MUX DERIV +WRTLK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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