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9ZML1233EKILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
13©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Power Connections (9ZML12xxE)
Power Connections (for pin-compatibility with 9ZML12xxB)
PLL Operating Mode
Note: PLL is off in Bypass Mode.
Skew Programming
Pin Number
Description
V
DD
V
DDIO
GND
1 2 Analog PLL
9 8 Analog input
28, 45, 64 40, 52 22, 27, 34, 39, 46, 51, 58, 63, 70 DIF clocks
Pin Number
Description
V
DD
V
DDIO
GND
1 2 Analog PLL
9 8 Analog input
28, 45, 64 21, 33, 40, 52, 57, 69
16, 22, 27, 34, 39, 46, 51, 58,
63, 70
DIF clocks
HIBW_BYPM_LOBW# Byte0[7:6]
Low (PLL Low BW) 00
Mid (Bypass) 01
High (PLL High BW) 11
Skew[2:0] Skew Steps Skew (ps)
000 0 0
001 1 -416.67
010 2 -833.33
011 3 -1250.00
100 4 -1666.67
101 5 -2083.33
110 6 -2500.00
111 7 -2916.67
14©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Figure 1. Skew Diagram
Test Loads
* Contact factory for versions of this device with Zo=100Ω.
Alternate Terminations
The LP-HCSL can easily drive other logic families. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's “Universal”
Low-Power HCSL Outputs” for details.
Table 13: Parameters for Low-Power HCSL Output Test Load
Device Rs (Ω) Zo (Ω) L (inches) C
L
(pF)
9ZML123x 27 85 12 2
9ZML123x 33 100 12 2
9ZML125x * Internal 85 12 2
9ZML125x * 7.5 100 12 2
DIF_INx
DIF_n
tSKEW_PLL
Rs
Rs
C
L
Differential Zo
C
L
Low-Power HCSL Output Test Load
(standard PCIe source -terminated test load )
Test
Points
L
15©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Clock Periods
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ accuracy
requirements (+/-100ppm). The buffer itself does not contribute to ppm error.
3
Driven by SRC output of main clock, 100MHz PLL Mode or Bypass Mode.
Table 14: Clock Periods – Differential Outputs with Spread Spectrum Disabled
SSC On
Center
Frequency
MHz
Measurement Window
Units Notes
1 Clock 1μs 0.1s 0.1s 0.1s 1μs 1 Clock
- c 2 c j i t t e r
AbsPer
Minimum
- S S C
Short-Term
Average
Minimum
- p p m
Long-Term
Average
Minimum
0 ppm
Period
Nominal
+ p p m
Long-Term
Average
Maximum
+ S S C
Short-Ter
m Average
Maximum
+ c 2 c j i t t e r
AbsPer
Maximum
DIF 100.00 9.94900
— 9.99900 10.00000 10.00100 — 10.05100 ns 1,2,3
Table 15: Clock Periods – Differential Outputs with Spread Spectrum Enabled
SSC On
Center
Frequency
MHz
Measurement Window
Units Notes
1 Clock 1μs 0.1s 0.1s 0.1s 1μs 1 Clock
- c 2 c j i t t e r
AbsPer
Minimum
- S S C
Short-Term
Average
Minimum
- p p m
Long-Term
Average
Minimum
0 ppm
Period
Nominal
+ p p m
Long-Term
Average
Maximum
+ S S C
Short-Ter
m Average
Maximum
+ c 2 c j i t t e r
AbsPer
Maximum
DIF 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2,3
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9ZML1233EKILF

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Buy 9ZML1233EKILF
Manufacturer:
IDT
Description:
Clock Buffer DB1200ZL OEM MUX DERIV +WRTLK
Lifecycle:
New from this manufacturer.
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