Rev. 1.3 19
Si8660/61/62/63
2.2. Eye Diagram
Figure 6 illustrates an eye-diagram taken on an Si8660. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8660 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 350 ps peak jitter were exhibited.
Figure 6. Eye Diagram
20 Rev. 1.3
Si8660/61/62/63
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 7, where UVLO+ and UVLO-
are the positive-going and negative-going thresholds respectively. Refer to Table 12 to determine outputs when
power supply (VDD) is not present.
Table 12. Si866x Logic Operation
V
I
Input
1,2
VDDI
State
1,3,4
VDDO
State
1,3,4
V
O
Output
1,2
Comments
HP P H
Normal operation.
LP P L
X
5
UP P
L
6
H
6
Upon transition of VDDI from unpowered to powered, V
O
returns to the same state as V
I
in less than 1 µs.
X
5
P UP Undetermined
Upon transition of VDDO from unpowered to powered, V
O
returns to the same state as V
I
within 1 µs.
Notes:
1. VDDI and VDDO are the input and output power supplies. V
I
and V
O
are the respective input and output terminals.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
4. “Unpowered” state (UP) is defined as VDD = 0 V.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
6. See "5. Ordering Guide" on page 26 for details. This is the selectable fail-safe operating mode (ordering option). Some
devices have default output state = H, and some have default output state = L, depending on the ordering part number
(OPN). For default high devices, the data channels have pull-ups on inputs/outputs. For default low devices, the data
channels have pull-downs on inputs/outputs.
Rev. 1.3 21
Si8660/61/62/63
3.1. Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following
this, the outputs follow the states of inputs.
3.2. Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. Both Side A and Side B each have their own
undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A
unconditionally enters UVLO when V
DD1
falls below V
DD1(UVLO–)
and exits UVLO when V
DD1
rises above
V
DD1(UVLO+)
. Side B operates the same as Side A with respect to its V
DD2
supply.
Figure 7. Device Behavior during Normal Operation
INPUT
V
DD1
UVLO-
V
DD2
UVLO+
UVLO-
UVLO+
OUTPUT
tSTART tSTART tSTART
tPHL
tPLH
tSD

SI8660BA-A-IS1

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Digital Isolators 6 Ch 1 kV Isolator 150M 6/0 NB
Lifecycle:
New from this manufacturer.
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