ZL30100 Data Sheet
11
Zarlink Semiconductor Inc.
3.0 Functional Description
The ZL30100 is a DS1/E1 System Synchronizer providing timing (clock) and synchronization (frame) signals to
interface circuits for DS1 and E1 Primary Rate Digital Transmission links, see Table 1. Figure 1 is a functional block
diagram which is described in the following sections.
3.1 Reference Select Multiplexer (MUX)
The ZL30100 accepts two simultaneous reference input signals and operates on their rising edges. One of them,
the primary reference (REF0) or the secondary reference (REF1) signal can be selected as input to the TIE
corrector circuit based on the reference selection (REF_SEL) input.
3.2 Reference Monitor
The input references are monitored by two independent reference monitor blocks, one for each reference. The
block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is
detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of
the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper
operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be
observed.
• Reference Frequency Detector: This detector determines whether the frequency of the reference clock is
8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz and provides this information to the various
monitor circuits and the phase detector circuit of the DPLL.
• Precise Frequency Monitor: This circuit determines whether the frequency of the reference clock is within
the applicable out-of-range limits selected by the OOR_SEL pin, see Figure 5, Figure 6 and Table 1. It will
take the precise frequency monitor up to 10 s to qualify or disqualify the input reference.
• Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of
approximately 30 μs to quickly detect large frequency changes.
• Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large phase
hits or the complete loss of the clock.
59 IC Internal Connection. Connect this pin to ground.
60 OOR_SEL Out Of Range Selection (Input). This pin selects the out of range reference rejection
limits, see Table 1 on page 17.
61 V
DD
Positive Supply Voltage. +3.3 V
DC
nominal.
62 NC No internal bonding Connection. Leave unconnected.
63 TIE_CLR
TIE Corrector Circuit Reset (Input). A logic low at this input resets the Time Interval
Error (TIE) correction circuit resulting in a realignment of the input phase with the output
phase.
64 BW_SEL Filter Bandwidth Selection (Input). This pin selects the bandwidth of the DPLL loop
filter, see Table 2 on page 18. Set continuously high to track jitter on the input reference
closely or set temporarily high to allow the ZL30100 to quickly lock to the input reference.
Pin Description (continued)
Pin # Name Description
