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ZL30100QDG1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
ZL30100 Data Sheet
List of Figures
4
Zarlink Semiconductor Inc.
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4 - Behaviour of the Dis/Requalify Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5 - DS1 Mode Out-of-Range Limits (OOR_SEL=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6 - E1 Mode Out-of-Range Limits (OOR_SEL=1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7 - Timing Diagram of Hitless Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8 - Timing Diagram of Hitless Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9 - DPLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10 - Mode Switching in Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11 - Reference Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15 - Timing Parameter Measurement Voltage Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16 - Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17 - Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
ZL30100 Data Sheet
5
Zarlink Semiconductor Inc.
1.0 Change Summary
Changes from February 2006 Issue to April 2010 Issue. Page, section, figure and table numbers refer to this
current issue.
Changes from November 2005 Issue to February 2006 Issue. Page, section, figure and table numbers refer to this
current issue.
Changes from July 2005 Issue to November 2005 Issue. Page, section, figure and table numbers refer to this
current issue.
Changes from September 2004 Issue to July 2005 Issue. Page, section, figure and table numbers refer to this
current issue.
Page Item Change
1 Ordering Information Box Leaded part number ZL30100QDC has been obsoleted and
replaced by ZL30100QDG1.
Page Item Change
1 Ordering Information Box Updated Ordering Information
Page Item Change
1 Features Added description for hitless reference switching.
23 Section 6.1 Removed power supply decoupling circuit and included
reference to synchronizer power supply decoupling application
note.
Page Item Change
9RST
pin Specified clock and frame pulse outputs forced to high
impedance
28 Table “DC Electrical Characteristics*“ Corrected Schmitt trigger levels
33 Table “Performance Characteristics* -
Functional“
Gave more detail on Lock Time conditions
ZL30100 Data Sheet
6
Zarlink Semiconductor Inc.
Changes from June 2004 Issue to September 2004 Issue. Page, section, figure and table numbers refer to this
current issue.
Page Item Change
1 Text Jitter changed to 0.6 ns from 0.5 ns
7 Figure 2 Added note specifying not e-Pad
8 Table “Pin Description“ Added information about Schmitt trigger feedback paths to
C1.5o, C2o, C16o
, and F8/F32o
11 Section 3.2 Added text about input pulse width restriction
16 Section 3.4 Added details to "Lock Indicator" on LOCK pin behaviour
20 Section 4.5 Added text and Figure 11 explaining LOCK pin behaviour
21 Section 5.0 Added Jitter definition
27 Table “Absolute Maximum Ratings*“ Corrected package power rating
28 Table “DC Electrical Characteristics*“ Corrected current consumption
Corrected input voltage characteristics to reflect Schmitt trigger
Corrected input leakage current to reflect internal pull-ups
Corrected output voltage note to reflect two pad strengths
29 Table “AC Electrical Characteristics* -
Input timing for REF0 and REF1
references (see Figure 16)“
Added explanatory note
34 Table “Performance Characteristics*:
Output Jitter Generation - ANSI
T1.403 Conformance“
Changed jitter numbers
34 Table “Performance Characteristics*:
Output Jitter Generation - ITU-T
G.812 Conformance“
Changed jitter number
34 Table “Performance Characteristics* -
Unfiltered Intrinsic Jitter“
Changed jitter numbers, removed UI column
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36

ZL30100QDG1

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Buy ZL30100QDG1
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Pb Free T1/E1 SYSTEM SYNCHRONIZER
Lifecycle:
New from this manufacturer.
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