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ZL30100QDG1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
ZL30100 Data Sheet
16
Zarlink Semiconductor Inc.
- 13 ns is the maximum phase discontinuity in the transition from the Holdover mode to the Normal mode
when a new TIE corrector value is calculated.
HMS=0: When the same ten Normal to Holdover to Normal mode changes occur and in each case Holdover mode
was entered for 2 seconds, then the overall MTIE would be 300 ns. As the delay value for the TIE corrector circuit is
not updated, there is no 13 ns measurement error at this point. The phase can still drift for 300 ns when the PLL is
in Holdover mode but when the PLL enters Normal mode again, the phase moves back to the original point so the
phase is not accumulated.
3.4 Digital Phase Lock Loop (DPLL)
The DPLL of the ZL30100 consists of a phase detector, a limiter, a loop filter, a digitally controlled oscillator (DCO)
and a lock indicator, as shown in Figure 9. The data path from the phase detector to the limiter is tapped and routed
to the lock indicator that provides a lock indication which is output at the LOCK pin.
Figure 9 - DPLL Block Diagram
Phase Detector - the phase detector compares the virtual reference signal from the TIE corrector circuit with the
feedback signal and provides an error signal corresponding to the phase difference between the two. This error
signal is passed to the limiter circuit.
Limiter - the limiter receives the error signal from the phase detector and ensures that the DPLL responds to all
input transient conditions with a maximum output phase slope of 61 μs/s or 9.5 ms/s, see Table 2.
Loop Filter - the loop filter is similar to a first order low pass filter with a narrow or wide bandwidth suitable to
provide system synchronization or line card timing, see Table 2. The wide bandwidth can be used to closely track
the input reference in the presence of jitter or it can be temporarily enabled for fast locking to a new reference (1 s
lock time).
Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the loop filter, and
based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is
dependent on the state of the ZL30100.
ZL30100 Data Sheet
17
Zarlink Semiconductor Inc.
In Normal mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Holdover mode, the DCO is free running at a frequency equal to the frequency that the DCO was generating in
Normal mode. The frequency in Holdover mode is calculated from frequency samples stored 26 ms to 52 ms before
the ZL30100 entered Holdover mode.
In Freerun mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source.
Lock Indicator - the lock detector monitors if the output value of the phase detector is within the phase-lock-
window for a certain time. The selected phase-lock-window guarantees the stable operation of the LOCK pin with
maximum network jitter and wander on the reference input. If the DPLL is locked and then goes into Holdover mode
(auto or manual), the LOCK pin will initially stay high for 1 s. If at that point the DPLL is still in holdover mode, the
LOCK pin will go low; subsequently the LOCK pin will not return high for at least the full lock-time duration. In
Freerun mode the LOCK pin will go low immediately.
3.5 Frequency Synthesizers
The output of the DCO is used by the frequency synthesizers to generate the C1.5o, C2o, C4o, C8o, C16o, C32o
and C65o
clocks and the F4o, F8o, F16o, F32o and F65o frame pulses which are synchronized to the selected
reference input (REF0 or REF1). The frequency synthesizers use digital techniques to generate output clocks and
advanced noise shaping techniques to minimize the output jitter. The clock and frame pulse outputs have limited
driving capability and should be buffered when driving high capacitance loads.
3.6 State Machine
As shown in Figure 1, the control state machine controls the TIE Corrector Circuit and the DPLL. The control of the
ZL30100 is based on the inputs MODE_SEL1:0, REF_SEL and HMS.
3.7 Master Clock
The ZL30100 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
4.0 Control and Modes of Operation
4.1 Out of Range Selection
The frequency out of range limits for the precise frequency monitoring in the reference monitors are selected by the
OOR_SEL pin, see Table 1.
OOR_SEL Application Applicable Standard Out Of Range Limits
0 DS1 ANSI T1.403
Telcordia GR-1244-CORE Stratum 4/4E
64 - 83 ppm
1E1 ITU-T G.703
ETSI ETS 300 011
100 - 130 ppm
Table 1 - Out of Range Limits Selection
ZL30100 Data Sheet
18
Zarlink Semiconductor Inc.
4.2 Loop Filter Selection
The loop filter settings can be selected through the BW_SEL pin, see Table 2.
4.3 Output Clock and Frame Pulse Selection
The output clock and frame pulses of the frequency synthesizers are available in two groups controlled by the
OUT_SEL input. Table 3 lists the supported combinations of output clocks and frame pulses.
4.4 Modes of Operation
The ZL30100 has three possible manual modes of operation; Normal, Holdover and Freerun. These modes are
selected with the mode select pins MODE_SEL1 and MODE_SEL0 as is shown in Table 4. Transitioning from one
mode to the other is controlled by an external controller.
4.4.1 Freerun Mode
Freerun mode is typically used when an independent clock source is required, or immediately following system
power-up before network synchronization is achieved.
In Freerun mode, the ZL30100 provides timing and synchronization signals which are based on the master clock
frequency (supplied to OSCi pin) only, and are not synchronized to the reference input signals.
The Freerun accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a
±32 ppm
output clock is required, the master clock must also be
±32 ppm. See Applications - Section 6.2, “Master Clock“ on
page 23.
BW_SEL Detected REF Frequency Loop Filter Bandwidth Phase Slope Limiting
0 any 1.8 Hz 61 μs/s
1 8 kHz 58 Hz 9.5 ms/s
1 1.544 MHz, 2.048 MHz,
8.192 MHz, 16.384 MHz
922 Hz 9.5 ms/s
Table 2 - Loop Filter Settings
OUT_SEL Generated Clocks Generated Frame Pulses
0 C1.5o, C2o, C4o
, C8o, C16o F4o, F8o, F16o
1 C1.5o, C2o, C16o, C32o, C65o F16o, F32o, F65o
Table 3 - Clock and Frame Pulse Selection
MODE_SEL1 MODE_SEL0 Mode
0 0 Normal (with automatic Holdover)
0 1 Holdover
10 Freerun
1 1 reserved (must not be used)
Table 4 - Operating Modes
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36

ZL30100QDG1

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