ZL30100QDG1 Datasheet ZL30100QDG1 | P19-P21

ZL30100 Data Sheet

Zarlink Semiconductor Inc.

4.4.2 Holdover Mode

Holdover mode is typically used for short durations while network synchronization is temporarily disrupted.

In Holdover mode, the ZL30100 provides timing and synchronization signals, which are not locked to an external

reference signal, but are based on storage techniques. The storage value is determined while the device is in

Normal Mode and locked to an external reference signal.

When in Normal mode, and locked to the input reference signal, a numerical value corresponding to the ZL30100

output reference frequency is stored alternately in two memory locations every 26 ms. When the device is switched

into Holdover mode, the value in memory from between 26 ms and 52 ms is used to set the output frequency of the

device. The frequency accuracy of Holdover mode is 0.15 ppm.

Two factors affect the accuracy of Holdover mode. One is drift on the master clock while in Holdover mode, drift on

the master clock directly affects the Holdover mode accuracy. Note that the absolute master clock (OSCi) accuracy

does not affect Holdover accuracy, only the change in OSCi accuracy while in Holdover mode. For example, a

±32 ppm master clock may have a temperature coefficient of ±0.1 ppm per °C. So a ±10 °C change in

temperature, while the ZL30100 is in Holdover mode may result in an additional offset (over the 0.15 ppm) in

frequency accuracy of

±1 ppm. Which is much greater than the 0.15 ppm of the ZL30100. The other factor affecting

the accuracy is large jitter on the reference input prior to the mode switch.

4.4.3 Normal Mode

Normal mode is typically used when a system clock source, synchronized to the network is required. In Normal

mode, the ZL30100 provides timing and frame synchronization signals, which are synchronized to one of the two

reference inputs (REF0 or REF1). The input reference signal may have a nominal frequency of 8 kHz, 1.544 MHz,

2.048 MHz, 8.192 MHz or 16.384 MHz. The frequency of the reference inputs are automatically detected by the

reference monitors.

When the ZL30100 comes out of RESET while Normal mode is selected by its MODE_SEL pins then it will initially

go into Holdover mode and generate clocks with the accuracy of its free running local oscillator (see Figure 10). If

the ZL30100 determines that its selected reference is disrupted (see Figure 3), it will remain in Holdover until the

selected reference is no longer disrupted or the external controller selects another reference that is not disrupted. If

the ZL30100 determines that its selected reference is not disrupted (see Figure 3) then the state machine will cause

the DPLL to recover from Holdover via one of two paths depending on the logic level at the HMS pin. If HMS=0 then

the ZL30100 will transition directly to Normal mode and it will align its output signals with its selected input

reference (see Figure 8). If HMS=1 then the ZL30100 will transition to Normal mode via the TIE correction state and

the phase difference between the output signals and the selected input reference will be maintained.

When the ZL30100 is operating in Normal mode, if it determines that its selected reference is disrupted (Figure 3)

then its state machine will cause it to automatically go to Holdover mode. When the ZL30100 determines that its

selected reference is not disrupted then the state machine will cause the DPLL to recover from Holdover via one of

two paths depending on the logic level at the HMS pin (see Figure 10). If HMS=0 then the ZL30100 will transition

directly to Normal mode and it will align its output signals with its input reference (see Figure 8). If HMS=1 then the

ZL30100 will transition to Normal mode via the TIE correction state and the phase difference between the output

signals and the input reference will be maintained.

If the reference selection changes because the value of the REF_SEL1:0 pins changes, the ZL30100 goes into

Holdover mode and returns to Normal mode through the TIE correction state regardless of the logic value on HMS

pin.

The ZL30100 provides a wide bandwidth loop filter setting (BW_SEL=1), which enables the PLL to lock to an

incoming reference in approximately 1 s.

ZL30100 Data Sheet

Zarlink Semiconductor Inc.

Figure 10 - Mode Switching in Normal Mode

4.5 Reference Selection

The active reference input (REF0, REF1) is selected by the REF_SEL pin as shown in Table 5. If the logic value of

the REF_SEL pin is changed when the DPLL is in Normal mode, the ZL30100 will perform a hitless reference

switch.

When the REF_SEL inputs are used to force a change from the currently selected reference to another reference,

the action of the LOCK output will depend on the relative frequency and phase offset of the old and new references.

Where the new reference has enough frequency offset and/or TIE-corrected phase offset to force the output

outside the phase-lock-window, the LOCK output will de-assert, the lock-qualify timer is reset, and LOCK will stay

de-asserted for the full lock-time duration. Where the new reference is close enough in frequency and TIE-

corrected phase for the output to stay within the phase-lock-window, the LOCK output will remain asserted through

the reference-switch process.

REF_SEL

(input pin)

Input Reference Selected

0REF0

1REF1

Table 5 - Reference Selection

REF_DIS=1: Current selected reference disrupted (see Figure 3). This is an internal signal.

REF_CH= 1: Reference change, a change in the REF_SEL pin. This is an internal signal.

TIE Correction

(HOLDOVER=1)

Holdover

(HOLDOVER=1)

REF_DIS=0

REF_CH=1

REF_DIS=0 and

REF_DIS=1

(REF_DIS=0 and HMS=1) or

REF_CH=1

REF_DIS=1

RST

REF_CH=0 and

HMS=0

Normal

(HOLDOVER=0)

ZL30100 Data Sheet

Zarlink Semiconductor Inc.

Figure 11 - Reference Switching in Normal Mode

5.0 Measures of Performance

The following are some PLL performance indicators and their corresponding definitions.

5.1 Jitter

Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander

is defined as the low-frequency variation of the clock edges from their ideal positions in time. High and low

frequency variation imply phase oscillation frequencies relative to some demarcation frequency. (Often 10 Hz or

20 Hz for DS1 or E1, higher for SONET/SDH clocks.) Jitter parameters given in this data sheet are total timing jitter

numbers, not cycle-to-cycle jitter.

5.2 Jitter Generation (Intrinsic Jitter)

Generated jitter is the jitter produced by the PLL and is measured at its output. It is measured by applying a

reference signal with no jitter to the input of the device, and measuring its output jitter. Generated jitter may also be

measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the

output jitter of the device. Generated jitter is usually measured with various bandlimiting filters depending on the

applicable standards.

5.3 Jitter Tolerance

Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the

presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied

jitter magnitude and jitter frequency depends on the applicable standards.

5.4 Jitter Transfer

Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter

at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured

with various filters depending on the applicable standards.

For the Zarlink digital PLLs two internal elements determine the jitter attenuation; the internal low pass loop filter

and the phase slope limiter. The phase slope limiter limits the output phase slope to, for example, 61 μs/s.

Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the

maximum output phase slope will be limited (i.e., attenuated).

Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for

large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter

signals (for example 75% of the specified maximum tolerable input jitter).

REF1REF0

REF_SEL

LOCK

Lock Time

Note: LOCK pin behaviour depends on phase and frequency offset of REF1.

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