Philips Semiconductors Preliminary data
P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family
8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM
2002 Jul 18
34
Programmable Counter Array (PCA)
The Programmable Counter Array available on the
P89C51RA2/RB2/RC2/RD2xx is a special 16-bit Timer that has five
16-bit capture/compare modules associated with it. Each of the
modules can be programmed to operate in one of four modes: rising
and/or falling edge capture, software timer, high-speed output, or
pulse width modulator. Each module has a pin associated with it in
port 1. Module 0 is connected to P1.3 (CEX0), module 1 to P1.4
(CEX1), etc. The basic PCA configuration is shown in Figure 25.
The PCA timer is a common time base for all five modules and can
be programmed to run at: 1/6 the oscillator frequency, 1/2 the
oscillator frequency, the Timer 0 overflow, or the input on the ECI pin
(P1.2). The timer count source is determined from the CPS1 and
CPS0 bits in the CMOD SFR as follows (see Figure 28):
CPS1 CPS0 PCA Timer Count Source
0 0 1/6 oscillator frequency (6-clock mode);
1/12 oscillator frequency (12-clock mode)
0 1 1/2 oscillator frequency (6-clock mode);
1/4 oscillator frequency (12-clock mode)
1 0 Timer 0 overflow
1 1 External Input at ECI pin
In the CMOD SFR are three additional bits associated with the PCA.
They are CIDL which allows the PCA to stop during idle mode,
WDTE which enables or disables the watchdog function on
module 4, and ECF which when set causes an interrupt and the
PCA overflow flag CF (in the CCON SFR) to be set when the PCA
timer overflows. These functions are shown in Figure 26.
The watchdog timer function is implemented in module 4 (see
Figure 35).
The CCON SFR contains the run control bit for the PCA and the
flags for the PCA timer (CF) and each module (refer to Figure 29).
To run the PCA the CR bit (CCON.6) must be set by software. The
PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when
the PCA counter overflows and an interrupt will be generated if the
ECF bit in the CMOD register is set, The CF bit can only be cleared
by software. Bits 0 through 4 of the CCON register are the flags for
the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set
by hardware when either a match or a capture occurs. These flags
also can only be cleared by software. The PCA interrupt system
shown in Figure 27.
Each module in the PCA has a special function register associated
with it. These registers are: CCAPM0 for module 0, CCAPM1 for
module 1, etc. (see Figure 30). The registers contain the bits that
control the mode that each module will operate in. The ECCF bit
(CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module)
enables the CCF flag in the CCON SFR to generate an interrupt
when a match or compare occurs in the associated module. PWM
(CCAPMn.1) enables the pulse width modulation mode. The TOG
bit (CCAPMn.2) when set causes the CEX output associated with
the module to toggle when there is a match between the PCA
counter and the module’s capture/compare register. The match bit
MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter
and the module’s capture/compare register.
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5)
determine the edge that a capture input will be active on. The CAPN
bit enables the negative edge, and the CAPP bit enables the positive
edge. If both bits are set both edges will be enabled and a capture will
occur for either transition. The last bit in the register ECOM
(CCAPMn.6) when set enables the comparator function. Figure 31
shows the CCAPMn settings for the various PCA functions.
There are two additional registers associated with each of the PCA
modules. They are CCAPnH and CCAPnL and these are the
registers that store the 16-bit count when a capture occurs or a
compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output.
MODULE FUNCTIONS:
16-BIT CAPTURE
16-BIT TIMER
16-BIT HIGH SPEED OUTPUT
8-BIT PWM
WATCHDOG TIMER (MODULE 4 ONLY)
MODULE 0
MODULE 1
MODULE 2
MODULE 3
MODULE 4
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3
P1.7/CEX4
16 BITS
PCA TIMER/COUNTER
TIME BASE FOR PCA MODULES
16 BITS
SU00032
Figure 25. Programmable Counter Array (PCA)
Philips Semiconductors Preliminary data
P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family
8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM
2002 Jul 18
35
CF CR CCF4 CCF3 CCF2 CCF1 CCF0––
CCON
(C0H)
CH CL
OVERFLOW
INTERRUPT
16–BIT UP COUNTER
IDLE
TO PCA
MODULES
CMOD
(C1H)
CIDL WDTE –– –– –– CPS1 CPS0 ECF
OSC/6 (6 CLOCK MODE)
OR
OSC/12 (12 CLOCK MODE)
TIMER 0 OVERFLOW
EXTERNAL INPUT
(P1.2/ECI)
DECODE
00
01
10
11
SU01256
OSC/2 (6 CLOCK MODE)
OR
OSC/4 (12 CLOCK MODE)
Figure 26. PCA Timer/Counter
MODULE 0
MODULE 1
MODULE 2
MODULE 3
MODULE 4
PCA TIMER/COUNTER
CF CR CCF4 CCF3 CCF2 CCF1 CCF0––
CMOD.0 ECF
CCAPMn.0 ECCFn
TO
INTERRUPT
PRIORITY
DECODER
CCON
(C0H)
IE.6
EC
IE.7
EA
SU01097
Figure 27. PCA Interrupt System
Philips Semiconductors Preliminary data
P89C51RA2/RB2/RC2/RD2xx80C51 8-bit Flash microcontroller family
8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM
2002 Jul 18
36
CMOD Address = D9H
Reset Value = 00XX X000B
CIDL WDTE CPS1 CPS0 ECF
Bit:
Symbol Function
CIDL Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.
WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.
Not implemented, reserved for future use.*
CPS1 PCA Count Pulse Select bit 1.
CPS0 PCA Count Pulse Select bit 0.
CPS1 CPS0 Selected PCA Input**
0 0 0 Internal clock, f
OSC
/6 in 6-clock mode (f
OSC
/12 in 12-clock mode)
0 1 1 Internal clock, f
OSC
/2 in 6-clock mode (f
OSC
/4 in 12-clock mode)
1 0 2 Timer 0 overflow
1 1 3 External clock at ECI/P1.2 pin
(max. rate = f
OSC
/4 in 6-clock mode, f
OCS
/8 in 12-clock mode)
ECF PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
** f
OSC
= oscillator frequency
SU01318
76543210
Figure 28. CMOD: PCA Counter Mode Register
CCON Address = D8H
Reset Value = 00X0 0000B
CF CR CCF4 CCF3 CCF2 CCF1 CCF0
Bit Addressable
Bit:
Symbol Function
CF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
CR PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
Not implemented, reserved for future use*.
CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01319
76543210
Figure 29. CCON: PCA Counter Control Register

P89C51RD2BBD/01,55

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 64KB FLASH 44LQFP
Lifecycle:
New from this manufacturer.
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