10 DS564F2
CS5341
Confidential Draft
3/11/08
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V, all voltages with respect to 0 V. MCLK=12.288 MHz; Master Mode)
9. Power-Down Mode is defined as RST
= Low, with all clocks and data lines held static at a valid logic
levels.
10. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram.
DIGITAL CHARACTERISTICS
Parameter Symbol Min Typ Max Unit
DC Power Supplies: Positive Analog
Positive Digital
Positive Logic
VA
VD
VL
3.1
3.1
1.7
-
-
-
5.25
5.25
5.25
V
V
V
Power Supply Current VA = 5 V
(Normal Operation) VA = 3.3 V
VL,VD = 5 V
VL,VD = 3.3 V
I
A
I
A
I
D
I
D
-
-
-
-
21
18.2
15
9
25.5
22.5
18.5
10
mA
mA
mA
mA
Power Supply Current VA = 5 V
(Power-Down Mode) (Note 9) VL,VD=5 V
I
A
I
D
-
-
1.5
0.4
-
-
mA
mA
Power Consumption VL, VD, VA = 5 V
(Normal Operation) VL, VD, VA = 3.3 V
(Power-Down Mode)
-
-
-
-
-
-
180
90
9.5
220
107.2
-
mW
mW
mW
Power Supply Rejection Ratio (1 kHz) (Note 10)
PSRR - 65 - dB
V
Q
Nominal Voltage
Output Impedance
-
-
VA÷2
25
-
-
V
k
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
-
-
VA
36
0.01
-
-
-
V
k
mA
Parameter Symbol Min Typ Max Units
High-Level Input Voltage (% of VL) V
IH
70% - - V
Low-Level Input Voltage (% of VL) V
IL
--30%V
High-Level Output Voltage at I
o
= 100 µA(% of VL)
V
OH
70% - - V
Low-Level Output Voltage at I
o
=100 µA(% of VL)
V
OL
--15%V
Input Leakage Current I
in
-10 - +10 µA
DS564F2 11
CS5341
Confidential Draft
3/11/08
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic "0" = GND = 0 V; Logic "1" = VL, C
L
= 20 pF)
11. For a description of speed modes, please refer to Table on page 15.
Parameter Symbol Min Typ Max Unit
MCLK Specifications
MCLK Period
t
clkw
39 - 45 ns
78 - 1953 ns
MCLK Pulse Duty Cycle
40 - 60 %
Master Mode
SCLK falling to LRCK Single-Speed
t
mslr
-20 - 20 ns
Double-Speed
-20 - 20 ns
Quad-Speed
-8 - 8 ns
SCLK falling to SDOUT valid. t
sdo
- - 32 ns
SCLK Duty Cycle. Single-Speed - 50 - %
Double-Speed
-50-%
Quad-Speed
-33-%
Slave Mode
Single-Speed (Note 11)
LRCK Duty Cycle
40 50 60 %
SCLK Period
t
sclkw
156 - - ns
SCLK Duty Cycle
45 50 55 %
SDOUT valid before SCLK rising
t
stp
10 - - ns
SDOUT valid after SCLK rising
t
hld
5--ns
SCLK falling to LRCK edge
t
slrd
-20 - 20 ns
Double-Speed (Note 11)
LRCK Duty Cycle
40 50 60 %
SCLK Period
t
sclkw
156 - - ns
SCLK Duty Cycle
45 50 55 %
SDOUT valid before SCLK rising
t
stp
10 - - ns
SDOUT valid after SCLK rising
t
hld
5--ns
SCLK falling to LRCK edge. t
slrd
-20 - 20 ns
Quad-Speed (Note 11)
LRCK Duty Cycle
40 50 60 %
SCLK Period
t
sclkw
78 - - ns
SCLK Duty Cycle
29.7 33 50 %
SDOUT valid before SCLK rising
t
stp
10 - - ns
SDOUT valid after SCLK rising
t
hld
5--ns
SCLK falling to LRCK edge. t
slrd
-8 - 8 ns
12 DS564F2
CS5341
Confidential Draft
3/11/08
SCLK output
t
mslr
SDOUT
t
sdo
LRCK output
MSB MSB-1
Figure 13. Master Mode, Left-Justified SAI Figure 14. Slave Mode, Left-Justified SAI
LRCK input
SCLK input
SDOUT
MSB
t
stp
t
hld
t
sclkw
MSB-1
t
slrd
Figure 15. Master Mode, I²S SAI Figure 16. Slave Mode, I²S SAI
SCLK output
t
mslr
t
sdo
LRCK output
MSB
SDOUT
LRCK input
SCLK input
SDOUT
t
stp
t
hld
t
sclkw
MSB
t
slrd

CS5341-DZZR

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Audio A/D Converter ICs IC 105dB 192 kHz Multi-bit Audio ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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