MC13201 Technical Data, Rev. 1.3,
Freescale Semiconductor 25
Table 10 summarizes the operation of the RF interface control bits.
8.7 RF Control Output CT_Bias
CT_Bias is a useful signal for interface with external RF components. It must be enabled via the ct_bias_en
control bit, and then its state is determined first by the selected RF mode and then by the active state of the
radio, i.e., whether a TX or RX operation is active:
Single Port Operation - In this mode, the CT_Bias can be used to establish the proper DC bias
voltage to a balun depending on the RX state versus TX state as described in Section 8.5.1, “Single
Port Operation. Note that in single port operation, the ct_bias_inv has no effect and CT_Bias is at
VDDA for TX and is at ground for RX.
Dual Port Operation - In this mode, the CT_Bias can be used as a control signal to enable a LNA
or PA or to determine the direction of an antenna switch as described in Section 8.5.2, “Dual Port
Operation. In dual port operation, ct-bias_inv is used to control the sense of the output control, i.e.,
CT_Bias can be active high or active low for TX and vice-versa for RX.
Table 11 defines the CT_Bias output state depending on control bits and operation mode of the modem.
Note that the output state is also defined in Idle, Hibernate, and Doze state as well as RX and TX operation.
Table 10. RF Interface Control Bits
Bit Designation Default Operation
14 ct_bias_en 0 1 = CT_Bias enabled. Output state is defined by Table 11.
0 = CT_Bias disabled. Output state is tri-stated.
13 ct_bias_inv 0 The output state of CT_Bias under varying conditions is defined in Table 11. This bit only
has effect for dual port operation.
1 = CT_Bias inverted.
0 = CT_Bias not inverted
12 RF_switch_mode 0 1= Single Port Mode selected where RF switch is active and RFIN_M and RFIN_P and
bidirectional signals.
0 = Dual Port Mode selected where RFIN_M and RFIN_P are inputs only and PAO_P
and PAO_N are separate outputs.
(This is default operation).
Table 11. CT_Bias Output vs. Register Settings
Mode CT_Bias_en RF_switch_mode CT_Bias_inv CT_Bias
RX 1 1 0 0
RX 1 1 1 0
RX 1 0 0 0
RX 0 X X Hi-Z
RX 1 1 0 1
TX 1 1 0 1
TX 1 1 1 1
TX 1 0 0 1
MC13201 Technical Data, Rev. 1.3,
26 Freescale Semiconductor
8.8 RF Single Port Application with an F Antenna
Figure 16 shows a typical single port RF application in which part count is minimized and a printed copper
F antenna is used for low cost. Only the RFIN port of the MC13201 is required because the differential
port is bi-directional and uses the on-chip T/R switch. Matching to near 50 Ohms is accomplished with L1,
L2, L3, and the traces on the PCB. A balun transforms the differential signal to single-ended to interface
with the F antenna.
The proper DC bias to the RFIN_x (PAO_x) pins is provided through the balun. The CT_Bias pin provides
the proper bias voltage point to the balun depending on operation, that is, CT_Bias is at VDDA voltage for
transmit and is at ground for receive. CT_Bias is switched between these two voltages based on the
operation. Capacitor C2 provides some high frequency bypass to the DC bias point. The L3/C1 network
provides a simple bandpass filter to limit out-of-band harmonics from the transmitter.
Figure 16. RF Single Port Application with an F-Antenna
TX 1 0 1 0
TX 0 X X Hi-Z
Idle 1 X X 0
Idle 0 X X Hi-Z
Doze 1 X X 0
Doze 0 X X Hi-Z
Hibernate 1 X X 0 (Low-Z)
Hibernate 0 X X Hi-Z
OffXXXUnknown
Table 11. CT_Bias Output vs. Register Settings (continued)
Mode CT_Bias_en RF_switch_mode CT_Bias_inv CT_Bias
L2
6.8nH
5
1
6
2
3
4
Z1
LDB212G4005C-001
L3
3. 9 nH
C1
1.0pF
R1
0R
R2
0R
Not Mounted
1
2
5
3
4
J1
SMA_ed ge_R ec ep t a
c
C2
10pF
AN T1
F_Antenna
PAO_M
6
PAO_P
5
RFIN_P
2
RFIN_M
1
CT_Bias
3
U5
MC 1 3 2 0 x
L1
1.8nH
L4
1.8nH
MC13201 Technical Data, Rev. 1.3,
Freescale Semiconductor 27
9 Packaging Information
Figure 17. Outline Dimensions for QFN-32, 5x5 mm
(Case 1311-03, Issue E)
N
EXPOSED DIE
ATTACH PAD
2.95
25
8
1
32
3.25
32X
0.18
0.30
24
17
16 9
0.5
M
0.1
C
M
0.05
C
A B
32X
0.5
0.3
C
0.1 A B
C
0.1 A B
VIEW M-M
0.25
28X
DETAIL M
PIN 1 INDEX
2.95
3.25
PIN 1
INDEX AREA
5
B
C
0.1
2X
2X
C
0.1
A
5
G
M
M
1.0
1.00
0.05
C0.1
C0.05
C
SEATING PLANE
5
DETAIL G
VIEW ROTATED 90° CLOCKWISE
(0.5)
(0.25)
0.8
0.75
0.00
(1.73)
(0.25)
0.065
32X
0.015
(45 )
5
4
PREFERRED CORNER CONFIGURATION
DETAIL N
0.60
0.24
0.60
0.24
4
DETAIL N
CORNER CONFIGURATION OPTION
DETAIL T
DETAIL M
BACKSIDE PIN 1 INDEX OPTION
DETAIL T
BACKSIDE PIN 1 INDEX OPTION
(90 )
5
2X
2X
0.39
0.31
0.1
0.0
DETAIL M
BACKSIDE PIN 1 INDEX OPTION
1.6
0.475
0.425
1.5
BACKSIDE
PIN 1 INDEX
0.25
0.15
R
DETAIL S
DETAIL M
PREFERRED BACKSIDE PIN 1 INDEX
0.217
0.137
(0.25)
0.217
0.137
(0.1)
DETAIL S
PREFERRED BACKSIDE PIN 1 INDEX
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF-PQFP-N.
4. CORNER CHAMFER MAY NOT BE PRESENT.
DIMENSIONS OF OPTIONAL FEATURES ARE FOR
REFERENCE ONLY.
5. COPLANARITY APPLIES TO LEADS, CORNER
LEADS, AND DIE ATTACH PAD.
6. FOR ANVIL SINGULATED QFN PACKAGES,
MAXIMUM DRAFT ANGLE IS 12°.

MC13201FC

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
RF Transceiver TORO IC NON 802.15.4
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet