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L9954

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
Electrical specifications L9954 / L9954XP
16/37 Doc ID 14279 Rev 4
Figure 3. SPI - transfer timing diagram
Figure 4. SPI - input timing
12345670
01
12345670
12345670
01
01
CSN
CLK
DI
DO
Input
Data
Register
CSN high to low: DO enabled
time
DI: data will be accepted on the rising edge of CLK signal
time
time
time
time
DO: data will change on the falling edge of CLK signal
fault bit
CSN low to high: actual data is
transfered to output power switches
old data new data
232221201918
232221201918
232221201918
X
X
XX
XX
12345670
01
12345670
12345670
01
12345670
12345670
01
01
CSN
CLK
DI
DO
Input
Data
Register
CSN high to low: DO enabled
time
DI: data will be accepted on the rising edge of CLK signal
time
time
time
time
DO: data will change on the falling edge of CLK signal
fault bit
CSN low to high: actual data is
transfered to output power switches
old data new data
12345670
01
01
CSN
CLK
DI
DO
Input
Data
Register
CSN high to low: DO enabled
time
DI: data will be accepted on the rising edge of CLK signal
time
time
time
time
DO: data will change on the falling edge of CLK signal
fault bit
CSN low to high: actual data is
transfered to output power switches
old data new data
232221201918
232221201918
232221201918
X
X
XX
XX
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
Valid
Val id
CSN
CLK
DI
t
set CSN
t
CLKH
t
set CLK
t
CLKL
t
hold DI
t
set DI
L9954 / L9954XP Electrical specifications
Doc ID 14279 Rev 4 17/37
Figure 5. SPI - DO valid data delay time and valid time
Figure 6. SPI - DO enable and disable time
0
.
8
V
CC
0
.
8
V
CC
0
.
8
V
CC
0
.
2
V
C
C
0
.
2
V
C
C
0
.
2
V
CC
C
L
K
DO
(
l
o
w
t
o
h
i
g
h
)
DO
(high
to lo
w
)
0
.
5
V
CC
t
r in
t
r
D
O
t
f
DO
t
d DO
t
f
i
n
CSN
t
f in r in
t
DO
DO
en DO tri L
t t
dis DO L tri
50%
0.8 VCC
0.2 VCC
50%
50%
en DO tri H
t t
dis DO H tri
C = 100 pF
L
C = 100 pF
L
pull-up load to VCC
pull-down load to GND
Electrical specifications L9954 / L9954XP
18/37 Doc ID 14279 Rev 4
Figure 7. SPI - driver turn on / off timing, minimum CSN HI time
Figure 8. SPI - timing of status bit 0 (fault condition)
CSN
dON
t
20%
80%
t
r in
f in
t
OFF
t
dOFF
t
OFF state
ON state OFF state
ON state
ON
t
output current
of a driver
50%
50%
80%
20%
20%
80%
50%
output current
of a driver
CSN low to high: data from shift register
is transferred to output power switches
t
CSN_HI,min
CSN
CLK
DI
DO
CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO
DI: data is not accepted
DO: status information of data bit 0 (fault condition) will stay as long as CSN is low
time
time
time
time
0
-
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

L9954

Mfr. #:
Buy L9954
Manufacturer:
STMicroelectronics
Description:
IC DVR DOOR ACTUATOR POWERSO-36
Lifecycle:
New from this manufacturer.
Delivery:
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