MT9V124
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23
Table 16. LVDS OUTPUT PORT DC SPECIFICATIONS (continued)
UnitsMaxTypMinConditionsSymbolParameter
Propagation Delay
t
p
C
load
= 6pF
2.5 ns
Differential Skew
t
skew
C
load
= 6pF
πΩ
Table 17. TWO-WIRE SERIAL INTERFACE TIMING DATA
(
f
EXTCLK = 22 MHz; V
DD
= 1.8 V; V
DD
_IO = 1.8 V; V
AA
= 2.8 V; V
AA
_PIX = 2.8 V; V
DD
_PLL = 2.8 V)
Parameter Symbol
Standard-Mode Fast-Mode
Unit
Min Max Min Max
SCLK Clock Frequency
f
SCL 0 100 0 400 KHz
Hold Time (repeated) START Condition.
After this Period, the First Clock Pulse is Generated
t
HD;STA 4.0 − 0.6 − μS
LOW Period of the SCLK Clock
t
LOW 4.7 − 1.3 − μS
HIGH Period of the SCLK Clock
t
HIGH 4.0 − 0.6 − μS
Set-up Time for a Repeated START Condition
t
SU;STA 4.7 − 0.6 − μS
Data Hold Time
t
HD;DAT 0
(Note 4)
3.45
(Note 5)
0
(Note 6)
0.9
(Note 5)
μS
Data Set-up Time
t
SU;DAT 250 − 100 (Note 6) − nS
Rise Time of Both SDATA and SCLK Signals
t
r − 1000 20 + 0.1Cb
(Note 7)
300 nS
Fall Time of Both SDATA and SCLK Signals
t
f − 300 20 + 0.1Cb
(Note 7)
300 nS
Set-up Time for STOP Condition
t
SU;STO 4.0 − 0.6 − μS
Bus Free Time between a STOP and START Condition
t
BUF 4.7 − 1.3 − μS
Capacitive Load for Each Bus Line Cb − 400 − 400 pF
Serial Interface Input Pin Capacitance CIN_SI − 3.3 − 3.3 pF
SDATA Max Load Capacitance CLOAD_SD − 30 − 30 pF
SDATA Pull-up Resistor RSD 1.5 4.7 1.5 4.7 KΩ
1. This table is based on I
2
C standard (v2.1 January 2000). On Semiconductor
2. Two-wire control is I
2
C−compatible
3. All values referred to V
IHmin
= 0.9 V
DD
and V
ILmax
= 0.1V
DD
levels. Sensor EXCLK = 22 MHz
4. A device must internally provide a hold time of at least 300 ns for the S
DATA signal to bridge the undefined region of the falling edge of SCLK.
5. The maximum
t
HD;DAT has only to be met if the device does not stretch the LOW period (
t
LOW) of the SCLK signal
6. A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system, but the requirement
t
SU;DAT 250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the S
CLK signal. If such a device does stretch the LOW period
of the S
CLK signal, it must output the next data bit to the SDATA line
t
r max +
t
SU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode
I
2
C-bus specification) before the SCLK line is released
7. Cb = total capacitance of one bus line in pF
