MT9V124
CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
www.onsemi.com
6
Table 4. Status of Output Signals During Reset and Standby
Signal Reset Post-Reset Standby
LVDS_P High−Z High−Z High−Z
LVDS_N High−Z High−Z High−Z
Module ID
The MT9V124 provides 4 bits of module ID that can be
read by the host processor from register 0x001A[15:12].
The module ID is programmed through the OTPM.
Image Data Output Interface
The High Speed LVDS output port on MT9V124 can
transmit the sensor image data to the host system over a
lengthy differential twisted pair cable.
The MT9V124 provides a serial high-speed output port,
which is able for driving standard IEEE 1596.3−1996 LVDS
receiver/deserializers such as the DS92LV1212A LVDS
Deserializer by National Semiconductor.
Image data is provided to the host system by the serial
LVDS interface. The Start bit, 8-bit image data, LV, FV, and
Stop bit are packetized in a 12-bit packet. The output
interface block can select either raw data or processed data.
Processed data format includes YCbCr, RGB-565, and
BT656 with odd SAV/EAV code. It also supports the SOC
Bypass 8 + 2 data format over the 12-bit packet.
The LVDS port is disabled when Hard Standby or Soft
Standby is asserted.
Sensor Control
The sensor core of the MT9V124 is a progressive-scan
sensor that generates a stream of pixel data at a constant
frame rate. Figure 4 shows a block diagram of the sensor
core. It includes the VGA active-pixel array. The timing and
control circuitry sequences through the rows of the array,
resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the
pixels in the row integrate incident light. The exposure is
controlled by varying the time interval between reset and
readout. Once a row has been selected, the data from each
column is sequenced through an analog signal chain,
including offset correction, gain adjustment, and ADC. The
final stage of sensor core converts the output of the ADC into
10-bit data for each pixel in the array.
The pixel array contains optically active and
light-shielded (dark) pixels. The dark pixels are used to
provide data for the offset-correction algorithms (black level
control).
The sensor core contains a set of control and status
registers that can be used to control many aspects of the
sensor behavior including the frame size, exposure, and gain
setting. These registers are controlled by the MCU firmware
and are also accessible by the host processor through the
two-wire serial interface.
The output from the sensor core is a Bayer pattern;
alternate rows are a sequence of either green and red pixels
or blue and green pixels. The offset and gain stages of the
analog signal chain provide per-color control of the pixel
data.
Figure 4. Sensor Core Block Diagram
Sensor Core
Control Registers System Control
10−Bit
Data Out
G1/G2
R/B
G1/G2
R/B
VGA
Active−Pixel
Sensor (APS)
Array
Analog
Processing
ADC
Digital
Processing
Timing
and
Control
Green1/Green2
Channel
Red/Blue
Channel
