CY51X7
High-Performance PLL Die for Oscillators
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-90233 Rev. *K Revised June 1, 2017
High-Performance PLL Die for Oscillators
Features
Low-noise PLL Die for integrated crystal applications
Differential clock output: Four frequencies selectable,
reconfigurable by I
2
C
Output frequency support from 15 MHz to 2.1 GHz
Fractional N PLL with fully integrated VCO
Works on third overtone (OT3) of a fixed-frequency crystal,
low-frequency fundamental (LFF), high-frequency
fundamental (HFF) mode crystal, and low-frequency input
LVPECL, CML, HCSL, LVDS, and LVCMOS output standards
available
Compatible with 3.3 V, 2.5 V, and 1.8 V supply
150 fs typical integrated jitter performance (12 kHz to 20 MHz
frequency offsets) for output greater than 150 MHz
VCXO functionality provided with tunable Total Pull Range
(TPR) from ±50 ppm to ±275 ppm
Die size facilitates integration with several integrated crystal
package options
Functional Description
The CY51X7 is a Programmable PLL-based crystal oscillator
solution with flexible output frequency options. It is field and
factory programmable for any output frequency between 15 MHz
and 2.1 GHz. Four frequencies are independently programmable
on the differential output with the frequency select (FS) bits.
Additionally, other frequency options can be configured with the
I
2
C interface. Using advanced design technology, it provides
excellent jitter performance across the entire output frequency
range working reliably at supply voltages from 1.8 V to 3.3 V for
junction temperatures from –40 °C to 125 °C. This makes it
ideally suited for communications applications (for example,
OTN, SONET/SDH, xDSL, GbE, Networking, Wireless
Infrastructure), test and instrumentation applications, and
high-speed data converters. Additionally, the VCXO function
enables the use of CY51X7 in applications requiring a clock
source with voltage control and in discrete clocking solutions for
synchronous timing applications.
The CY51X7 die configuration can be created using
ClockWizard 2.1. For programming support, contact Cypress
Technical Support or send an email to clocks@cypress.com.
For a complete list of related documentation, click here.
Logic Block Diagram
Crystal
Oscillator
Fractional - N
LC VCO Based PLL
Output
Dividers
Output
Drivers
Digital Configuration and Control
NVM
I
2
C
Interface
ADC + Digital Filtering Pathway
(for VCXO Function)
XOUT
XIN
FS[1:0]
SCL SDA VC OE
CLK_N
CLK_P
VDD GND
VDDO
CLK_SE
Document Number: 001-90233 Rev. *K Page 2 of 25
CY51X7
Contents
Die Pad Description ..........................................................3
Die Pad Summary .............................................................3
Functional Overview ........................................................4
Programmable Features .............................................. 4
Architecture Overview ................................................. 4
Internal State Diagram ................................................ 4
Small/Large Changes ..................................................5
Programming Support .................................................5
Frequency Configurations ........................................... 5
Programmable OE Polarity .......................................... 5
Programmable VCXO .................................................. 5
Power Supply Sequencing ..........................................5
I2C Interface ................................................................ 5
Memory Map ...............................................................6
Absolute Maximum Ratings ............................................7
Recommended Operating Conditions ............................7
DC Electrical Specifications ............................................7
DC Specifications for LVDS Output ................................8
DC Specifications for LVPECL Output ...........................8
DC Specifications for CML Output ..................................8
DC Specifications for HCSL Output ................................9
DC Specifications for LVCMOS Output ..........................9
VCXO Specific Parameters ..............................................9
AC Electrical Specifications for LVPECL,
LVDS, CML Outputs .......................................................10
AC Electrical Specifications for HCSL Output .............11
AC Electrical Specifications for LVCMOS Output .......11
HFF Crystal Specifications ............................................12
OT3 Crystal Specifications ............................................12
LFF Crystal Specifications ............................................12
LF Low Frequency Reference .......................................12
Timing Parameters .........................................................13
Input Clock Measurement Point ....................................13
Phase Jitter Characteristics ..........................................14
I2C Bus Timing Specifications ......................................14
Voltage and Timing Definitions .....................................15
Phase Noise Plots ..........................................................17
Ordering Information ......................................................20
Ordering Code Definitions ......................................... 20
Packaging Information ...................................................21
Acronyms ........................................................................22
Document Conventions .................................................22
Units of Measure ....................................................... 22
Document History Page .................................................23
Sales, Solutions, and Legal Information ......................25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC® Solutions ...................................................... 25
Cypress Developer Community ................................. 25
Technical Support ..................................................... 25
Document Number: 001-90233 Rev. *K Page 3 of 25
CY51X7
Note:
Die Size: X = 919.5955 Pm
Horizontal = 80 Pm
Scribe: Vertical = 79.8955 Pm
Y = 1399.4 Pm
Die Pad Description
FS1
OE
SDA
VC
GNDO
CLK_SE
CLK_P
CLK_N
VDDO
Y
X
Vertical Scribe
Horizontal Scribe
CY Logo
FS0_BOT
FS1_BOT
SDA_BOT
SCL_BOT
XIN
XOUT
GND
VDDA
SCL
FS0
Die Pad Summary
Pad coordinates are referenced from the seal ring edge (X = 0, Y = 0)
Name Die Pad X Coordinate (
P
m) Y Coordinate (
P
m) Description
VC 1 86.8275 1234.157 VIN for VCXO
SDA 2 86.8275 1133.357 Serial data input/output for I
2
C
FS1 3 86.8275 1032.557 Frequency Select input 1 (100 k: pull-down)
OE 4 86.8275 931.7565 Output Enable input (configurable 200 k:pull-up/ pull-down
FS0_BOT 5 162.063 87.2235 Frequency Select 0 (Alternative) (100 k: pull-down)
FS1_BOT 6 262.8765 87.2235 Frequency Select 1 (Alternative) (100 k: pull-down)
SDA_BOT 7 363.663 87.2235 Serial data input/output (Alternative)
SCL_BOT 8 464.463 87.2235 Serial clock input for I
2
C (Alternative)
V
DDO
9 714.627 73.0755 Power supply for output driver
CLK_N 10 714.627 173.8755 Complementary output
CLK_P 11 714.627 305.2755 True output
CLK_SE 12 714.627 393.4755 (Optional) LVCMOS clock output
GNDO 13 714.627 494.2755 Supply Ground for output driver
FS0 14 704.0025 1232.123 Frequency Select input 0 (100 k: pull-down)
SCL 15 603.2025 1232.123 Serial clock input for I
2
C
V
DDA
16 502.4025 1232.123 Power supply for core
GND 17 401.6025 1232.123 Power supply ground
XIN 18 300.8025 1232.123 Crystal reference input
XOUT 19 200.0025 1232.123 Crystal reference output
Note: CLK_SE and (CLK_P, CLK_N) will not be available at the same time. VDDA should equal VDDO.

CY5137-1X07I

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Clock Generators & Support Products Programmable Clocks
Lifecycle:
New from this manufacturer.
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