Document Number: 001-90233 Rev. *K Page 5 of 25
When the LOCK is programmed as “10” or “01”, the device goes
to the “Active state” and the output clock will be available after
completion of the power-on cycle.
In the “Active state”, you may change the output frequency by
applying “Small Change” or “Large Change” commands.
Figure 3. State Diagrams
Small/Large Changes
Small change refers to the case where the frequency is changing
within ±500 ppm. The frequency information can be loaded
through I
2
C and the output frequency will change without any
glitch from its original frequency to the new frequency.
Note The small change functionality is not supported in the
Integer mode PLL. For more information, see AC Electrical
Specifications for LVPECL, LVDS, CML Outputs.
Large change refers to the case where the frequency is changing
more than ±500 ppm and is done through an I
2
C or FS state
change. The device will recalibrate and reconfigure the PLL and
the output will be unstable until this process is completed.
Programming Support
The CY51X7 is a software-configurable solution in which
Cypress provides a programming specification that defines all
necessary configuration bits. The customer uses this information
to develop programming software for use with their programmer
hardware.
Frequency Configurations
The FS[0-3] setting is done based on the logic levels on the FS0
and FS1 pins as indicated in the Ta b le 2 . The frequency
configuration consists of the desired output frequency
corresponding to each of the FS[0–3] setting. The Fractional-N
PLL is loaded with values required to generate the frequency for
each of these settings based on the input crystal frequency. The
frequency configuration for FS[0–3] is provided in Table 4 on
page 6.
Programmable OE Polarity
The CY51X7 contains a bit for OE polarity setting (default is
active-low). You can choose active-high or active-low polarity for
the OE function. The output will be disabled when OE is
deasserted.
Programmable VCXO
The device incorporates a proprietary technique for modulating
frequency by modifying VCO frequency according to the VC
control voltage. The pull profile is linear and accurate compared
to pulling the OT3/HFF reference. Also, the VCXO
characteristics are very stable and do not vary over temperature,
supply voltage, or process variations.
Kv (slope for frequency versus VC), TPR VC bandwidth, and
VCXO on/off are all programmable. Note that the VCXO
functionality is not supported in the Integer mode PLL.
Power Supply Sequencing
For start-up, the CY51X7 does not require any specific
sequencing and only needs a monotonic V
DD
ramp specified in
the datasheet. After the ramp up, V
DD
has to be maintained
within the limits specified for it in the Recommended Operating
Conditions. Brownout detection and protection has to be
implemented elsewhere in the system.
Other input signals, such as VC, FS0 or FS1, can power up
earlier or later than V
DD
. There are no timing requirements for
those input signals with reference to V
DD
. The device will operate
normally when all of the input signals are settled in the configured
state.
If a TCXO or external clock is fed into the XIN/XOUT inputs, a
stable input has to be present before start of the V
DD
ramp-up to
the specified level. This is because the on-chip frequency
calibration process starts at Power ON and requires a stable
reference input to be available at the start of the process.
I
2
C Interface
The CY51X7 supports two-wire serial interface and I
2
C in Fast
Mode (400 kbps) and 7-bit addressing. The device address is
programmable and is 55h by default. It supports single-byte
access only. The first I
2
C access to the device has to be made
5 ms (minimum) after VDD reaches its minimum specified
voltage.
ReleaseResetonPower
Copy“eFuse”to“NVMCopy”
CommandWaitState
Activestate
OutputClock
LOCK=“00”
LOCK=“10”
CrystalBlanktuningstate
Exitcommand
XTͲPATTERN=“01”or“10”
XTͲPATTERN=“00”or“11”
LoopLock
SmallChange
LargeChange
Table 2. FS Setting
FS1 FS0 FS Setting
00FS0
01FS1
10FS2
11FS3
