Document Number: 001-90233 Rev. *K Page 7 of 25
Absolute Maximum Ratings
Exceeding maximum ratings
[1]
may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage to ground potential .............–0.5 V to + 3.8 V
Input voltage ...............................................–0.5 V to + 3.8 V
Storage temperature (non-condensing) ... –55 qC to +150 qC
Junction temperature ............................... –40 qC to +125 qC
Programming temperature ........................... 0 qC to +125 qC
Programming Voltage .........................................2.5V ±0.1 V
Supply Current for eFuse Programming ..................... 50 mA
Data retention at T
J
= 125 qC ...............................> 10 years
Maximum programming cycles ............................................1
ESD HBM (JEDEC JS-001-2012) ............................ 2000 V
ESD MM (JEDEC JESD22-A115B) ............................. 200 V
Latch-up current .................................................... ± 140 mA
Recommended Operating Conditions
Parameter Description Min Max Unit
V
DD,
V
DDO
Supply voltage, 1.8-V operating range, 1.8 V ± 5% 1.71 1.89 V
Supply voltage, 2.5-V operating range, 2.5 V ± 10% 2.25 2.75 V
Supply voltage, 3.3-V operating range, 3.3 V ± 10% 2.97 3.63 V
f
RES
Frequency resolution – 2 ppb
T
PLLHOLD
PLL Hold Temperature Range 125 qC
DC Electrical Specifications
Parameter Description Test Conditions Min Typ Max Unit
I
DD
[2]
Supply current
[3]
, LVPECL
V
DD
= 3.3V, 2.5V,
50 : to V
TT
(V
DDO
– 2.0 V), with common
mode current
– 93 106
mA
Supply current
[3]
, LVPECL
V
DD
= 3.3V, 2.5V,
50 : to V
TT
(V
DDO
– 2.0 V), without
common mode current
[4]
–8194
Supply current
[3]
, LVDS
V
DD
= 3.3V, 2.5V, 1.8V,
100 : between CLKP and CLKN
–6981
Supply current
[3]
, HCSL
V
DD
= 3.3V, 2.5V, 1.8V,
33 : and 49.9 : to GND
–8093
Supply current
[3]
, CML
V
DD
= 3.3V, 2.5V, 1.8V,
50 : to V
DDO
–7386
Supply current
[3]
, CMOS
V
DD
= 3.3 V, 2.5 V, 1.8 V,
0 pF load, 33.33 MHz
–5870
Supply current
[3]
, CMOS
V
DD
= 3.3 V, 2.5 V, 1.8 V,
10 pF load, 33.33 MHz
–6678
Supply current, PLL only V
DD
= 3.3V, 2.5V, 1.8V – 59 70
I
IH
Input high current Logic input, Input = V
DD
–3050μA
I
IL
Input low current Logic input, Input = GND – 30 50 μA
V
IH
[5]
Input high voltage OE, FS, SCL, SDA logic level = 1 0.7 × V
DD
––V
V
IL
[5]
Input low voltage OE, FS, SCL, SDA logic level = 0 – – 0.3 × V
DD
V
V
IN
Input voltage level All input, relative to GND –0.5 – 3.8 V
R
P
Internal pull-up resistance OE, configured active High – 200 – k:
R
D
Internal pull-down resistance
OE, configured active Low – 200 – k:
FS0, FS1 pins – 100 – k:
Notes
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation
of the device at these or at any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to
Absolute-Maximum-Rated conditions for extended periods may affect device reliability or cause permanent device damage.
2. I
DD
is the total supply current and is measured with V
DD
and V
DDO
shorted together.
3. Maximum current 3 mA lesser with HFF Crystal.
4. In ClockWizard 2.1, setting the output standard to LVPECL2 configures the output to "LVPECL without common mode current". Refer to AN210253 for LVPECL
terminations for different use case configurations.
5. I
2
C operation applicable for V
DD
of 1.8 V and 2.5 V only.
