Document Number: 001-90233 Rev. *K Page 10 of 25
CY51X7
AC Electrical Specifications for LVPECL, LVDS, CML Outputs
(V
DD
= 3.3 V and 2.5 V for LVPECL, with common mode current, and V
DD
= 3.3 V, 2.5 V, and 1.8 V for LVDS and CML outputs)
Parameter
[9]
Description Details/Conditions Min Typ Max Unit
f
OUT
Clock Output Frequency
LVPECL, CML, LVDS output
standards
15 2100 MHz
t
RF
LVPECL Output Rise/Fall Time
20% to 80% of AC levels.
Measured at 156.25 MHz for PECL
outputs.
350 ps
CML Output Rise/Fall Time
20% to 80% of AC levels.
Measured at 156.25 MHz for CML
outputs.
350 ps
LVDS Output Rise/Fall Time
20% to 80% of AC levels.
Measured at 156.25 MHz for LVDS
outputs.
350 ps
t
ODC
Output Duty Cycle
Measured at differential 50% level,
156.25 MHz.
45 50 55 %
V
P
LVDS output differential peak 15 MHz to 700 MHz 247 454 mV
V
P
LVDS output differential peak 700 MHz to 2100 MHz 150 454 mV
'V
P
Change in VP between
complementary output states
50 mV
V
P
LVPECL output differential peak
f
OUT
= 15 MHz to 325 MHz 450 mV
V
P
f
OUT
= 325 MHz to 700 MHz 350 mV
V
P
f
OUT
= 700 MHz to 2100 MHz 250 mv
V
P
CML output differential peak f
OUT
= 15 MHz to 700 MHz 250 600 mV
V
P
CML output differential peak f
OUT
= 700 MHz to 2100 MHz 200 600 mV
t
CCJ
Cycle to Cycle Jitter
pk, measured at differential signal,
156.25 MHz, over 10k cycles,
100 MHz–130 MHz crystal
50 ps
t
PJ
Period Jitter
pk-pk, measured at differential
signal, 156.25 MHz, over 10k
cycles, 100 MHz–130 MHz crystal
50 ps
J
RMS
RMS Phase Jitter
f
OUT
= 156.25 MHz, 12 kHz–20
MHz offset, non-VCXO mode
150 250 fs
Non-VCXO Mode
PN1k Phase Noise, 1 kHz Offset
100-130 MHz crystal reference,
f
OUT
= 156.25 MHz
-113
dBc/
Hz
PN10k Phase Noise, 10 kHz Offset
100-130 MHz crystal reference,
f
OUT
= 156.25 MHz
-127
dBc/
Hz
PN100k Phase Noise, 100 kHz Offset
100-130 MHz crystal reference,
f
OUT
= 156.25 MHz
-135
dBc/
Hz
PN1M Phase Noise, 1MHz Offset
100-130 MHz crystal reference,
f
OUT
= 156.25 MHz
-144
dBc/
Hz
PN10M Phase Noise, 10 MHz Offset
100-130MHz crystal reference,
f
OUT
= 156.25 MHz
–152
dBc/
Hz
PN-SPUR Spur
At frequency offsets equal to and
greater than the update rate of the
PLL
–65
dBc/
Hz
Note
9. Parameters are guaranteed by design and characterization. Not 100% tested in production.
Document Number: 001-90233 Rev. *K Page 11 of 25
CY51X7
AC Electrical Specifications for HCSL Output
Parameter
[10]
Description Test Conditions Min Typ Max Units
f
OUT
Output frequency HCSL 15 700 MHz
E
R
Rising edge rate
Measured taken from differential
waveform, –150 mV to +150 mV
0.6 5.7
[11]
V/ns
E
F
Falling edge rate
Measured taken from differential
waveform, –150 mV to +150 mV
0.6 5.7
[11]
V/ns
t
STABLE
Time before voltage ring back
(VRB) is allowed
Measured taken from differential
waveform, –150 mV to +150 mV
500 ps
R-F
_MATCHING
Rise-Fall matching
Measured taken from
single-ended waveform, rising
edge rate to falling edge rate
matching, 100 MHz
–100 100 ps
t
DC
Output duty cycle
Measured taken from differential
waveform, f
OUT
= 100 MHz
45 55 %
t
CCJ
Cycle to cycle Jitter
Measured taken from differential
waveform, 100 MHz
50 ps
J
RMSPCIE
Random jitter, PCIE
Specification 3.0
100 MHz–130 MHz crystal 1
ps
(RMS
)
AC Electrical Specifications for LVCMOS Output
(Load: 10 pF < 100 MHz, 7.5 pF < 150 MHz, 5 pF > 150 MHz)
Parameter
[10]
Description Test Conditions Min Typ Max Unit
f
OUT
Output frequency 15 250 MHz
t
DC
Output duty cycle
Measured at 1/2 V
DDO
, loaded,
f
OUT
< 100 MHz
45 55 %
Measured at 1/2 V
DDO
, loaded,
f
OUT
> 100 MHz
40 60 %
t
RFCMOS
Rise/Fall time
V
DDO
= 1.8 V, 20%–80% 2 ns
V
DDO
= 2.5 V, 20%–80% 1.5 ns
V
DDO
= 3.3 V, 20%–80% 1.2 ns
t
CCJ
Cycle to cycle Jitter
pk, Measured at 1/2V
DDO
over 10k cycle,
f
OUT
= 156.25 MHz
50 ps
t
PJ
Period Jitter
pk, Measured at 1/2V
DDO
over 10k cycle,
f
OUT
= 156.25 MHz
100 ps
Notes
10. Parameters are guaranteed by design and characterization. Not 100% tested in production.
11. Edge rates are higher than 4 V/ns due to jitter performance requirements.
Document Number: 001-90233 Rev. *K Page 12 of 25
CY51X7
Note
12. Parameters are guaranteed by design and characterization. Not 100% tested in production.
HFF Crystal Specifications
Parameter
[12]
Description Test Conditions Min Typ Max Unit
f
XTAL
Crystal frequency range 100 130 MHz
C0 Crystal shunt capacitance 2 pF
CL Crystal load capacitance 5 pF
ESR
Crystal equivalent series
resistance
ESR = Rm (1 + C0/CL) ^ 2
Rm = Crystal motional resistance
–20–:
DL Drive level 200 PW
OT3 Crystal Specifications
Parameter
[12]
Description Test Conditions Min Typ Max Units
f
XTAL
Crystal frequency range 100 130 MHz
C0 Crystal shunt capacitance 2 pF
CL Crystal load capacitance 5 pF
ESR
Crystal equivalent series
resistance
ESR = Rm (1 + C0/CL) ^ 2
Rm = Crystal motional resistance
–6090:
DL Drive level 200 PW
LFF Crystal Specifications
Parameter
[12]
Description Test Conditions Min Typ Max Units
f
XTAL
Crystal frequency range 50 60 MHz
C0 Crystal shunt capacitance 2 pF
CL Crystal load capacitance 8 pF
ESR
Crystal equivalent series
resistance
ESR = Rm (1 + C0/CL) ^ 2
Rm = Crystal motional resistance
––90W
DL Drive level 200 PW
LF Low Frequency Reference
(TCXO reference input)
Parameter
[12]
Description Test Conditions Min Typ Max Units
f
IN
Input frequency 50 60 MHz
t
DC
Input duty cycle Measured at 1/2 input swing 40 60 %
V
PP
pk-pk input swing AC coupled input 0.8 1.2 V
V
IL
Input low voltage DC coupled input 0.2 V
V
IH
Input high voltage DC coupled input 0.8 1.2 V
t
R
Input rise time 20%–80% of input 1.5 ns
t
F
Input fall time 20%–80% of input 1.5 ns
PN
10K
Input phase noise 10-kHz offset –151
dBc/H
z
PN
100K
Input phase noise 100-kHz offset –155
dBc/H
z
PN
1M
Input phase noise 1-MHz offset –156
dBc/H
z

CY5137-1X07I

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Clock Generators & Support Products Programmable Clocks
Lifecycle:
New from this manufacturer.
Delivery:
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